Abstract: A digital phase synchronizing apparatus delays sequentially a clock signal output from an oscillator, generates a plurality of delayed clock signals, selects a delayed clock signal that is synchronized with horizontal synchronizing signal HS from among the delayed clock signals using a change point detection circuit, and selects the output signal. Meanwhile, fine delay circuit further delays sequentially the selected delayed clock signal, generates a plurality of delayed clock signals, and selects a delayed clock signal that corresponds to the setting of a rotary dip switch as the system clock, thereby to efficiently acquire phase synchronization of the clock signal with the input signal without being affected by the signal characteristics of the input signal.

Abstract: Provided is an image synthesizing device with which a specific display region P of a sub-image is synthesized and displayed within a specific display region Q of a main image displayed on a display 9, wherein this image synthesizing device comprises a frame memory with which the data in the synthesis and display region P out of the sub-image data is continuously stored in the order of input, after which the stored sub-image data is read out when the scanning address of the main image data is an address corresponding to the display region Q, and a selector 4 with which the main image data displayed on the display 9 and the sub-image data continuously and sequentially read out from the frame memory are inputted, and when the scanning address of the main image data is an address corresponding to the display region Q, the selected channel is switched from main image data to the sub-image data and outputted to the display 9 where this sub-image data is displayed, which allows the capacity of the frame memory used

Abstract: A display control device for displaying data stored in a video memory on a flat display such as an EL or liquid crystal display on the basis of display control signals output from a CRT control device, which comprises a memory means that allows data read and write operations to be executed simultaneously and that has a capacity to store at least one screen of display data for display on the flat display and display control means for alternately executing, in accordance with the display control signals, a first operation in which data corresponding to an upper half of the display screen are retrieved from the data stored in the video memory and sequentially output to an upper region of the display, data corresponding to the upper half of the display screen are sequentially stored in the memory means, and data corresponding to a lower half of the display screen stored in the memory means are sequentially output to a lower region of the display, and a second operation in which data corresponding to the lower hal

Abstract: For arithmetically combining the values of two numbers, for example adding and subtracting, comprising a data deletion system for deleting values from input data and outputting the result. The system has a deletion number detection apparatus for finding a value on the basis of input data and output data, wherein an output data number setting device sets the bits of an output data number to be all "1" in logical value prior to sending that number to a down counter which subtracts the output number from the input number for the result.

Abstract: An image data memory control unit for storing the image data of a plurality of planes in a multiport video memory including a memory component having a random port for reading and writing data therethrough in response to input address signals and a register component having a serial port for outputting data that have been stored in the memory component serially in sequence from the lower address in synchronicity with input clock signals, comprises an image processor for outputting address signals in which the most significant bit portion is a plane recognition bit portion that recognizes the plurality of planes, and for outputting the image data of the plurality of planes therethrough to the multiport video memory in response to the address signals; and address conversion unit for converting the address signals output from the image processor so that the plane recognition bit portion is moved to the least significant bit portion, and the remaining bits are shifted to higher significant bits following the leas

Abstract: A serial controller in which nodes to which are connected one or plurality of sensors and one or a plurality of actuators are connected in series in the form of a closed loop including a main controller which sends data frame signals including a first special code, a second special code and output data for the actuators. The main controller measures and controls the time interval for sending the data frame signals and selecting a broken-line detection time setting in order to improve the transmission efficiency and to carry out the control in real time.

Abstract: An asynchronous data transmission system for asynchronously transmitting data from a first system controller to a second system controller in which a memory for holding therein data to be transmitted has a duplex structure including first and second memories, output data of the first system controller is alternately written into the first and second memories in response to the data transmission of the first system controller, the reading operation of the second system controller is carried out over one of the memories over which the writing operation of the first system controller has been completed, the next writing operation of the first system controller is carried out over the other one of the memories.

Abstract: A data input control device for a serial controller wherein a plurality of nodes each having one or a plurality of sensors connected thereto are serially connected to each other with a main controller included therein, the main controller delivers a predetermined data frame signal at a period sufficiently shorter than the variation interval of data detected by the nodes, and each node serves to add to the data frame signal the data from sensors connected to the node. The main controller compares the sensor data contained in the data frame signal inputted thereinto for predetermined times on receipt of a data frame signal, and takes thereinto the sensor data as true data only when the results derived from the comparisons performed by the predetermined times coincide with each other. Therefore, errors caused over the whole path through which the data outputted from the sensors are inputted into the main controller via the respective nodes can be detected.

Abstract: A serial controller in which nodes to which are connected one or a plurality of sensors and one or a plurality of actuators are connected in series in the form of a closed loop including a main controller which sends data frame signals including a first special code, a second special code and output data for the actuators. Each of the nodes adds the data received from its associated sensor to the end of the first special code and picks up the output data for its associated actuator from the end of the second special code. The main controller controls the interval for sending the data frame signals depending upon the number of sensors and the number of actuators detected based on the initial frame signal that includes the first special code, the second special code and data for detecting the number of actuators, in order to improve the transmission efficiency and to carry out the control in real time.

Abstract: An error display device of a data transmission system in which a plurality of nodes are connected to a main controller to transmit data, the main controller being adapted to discriminate an error content and an error position from an error signal contained in a data frame signal transmitted from the nodes and to display the error content and position. Since it is so arranged that the storage content of temporary memory for temporarily storing therein a signal corresponding to the error content and the error position is not updated each time the error signal is inputted but updated intermittently according to an operator's instruction, even when errors frequently take place at a multiplicity of locations, that is, even when it is difficult for an operator to confirm error display contents, the operator can reliably confirm the error contents.

Abstract: A serial control apparatus includes a main controller (2) and a plurality of nodes (3) each serving as an auxiliary controller normally serially arranged on a loop-shaped signal transmission line (1). Each node (3) extracts data for the present node among from the data delivered from the main controller (2) as time elapses so as to allow the terminal units (A) associated with the present node to be properly controlled. In addition, the node inserts the output data from the terminal units (A) into a time slot corresponding to the present node and then delivers to the signal transmission line (1) the output data which in turn are transferred to the main controller (2) via other nodes on the downstream side. To assure that the data extracting circuit operates properly, two latching circuits, i.e., first and second latching circuits (311, 312 to 315) are serially arranged in a signal passage by way of which the extracted data are fed to a driver (316) for the corresponding terminal units.

Abstract: This apparatus for carrying out serial control comprises a plurality of node controllers each including a group of sensors (21S to 2nS), a group of actuators (21A to 2nA) or the like terminal components and a main controller for controlling the node controllers and the terminal components in an annular configuration or in a daisychain-shaped configuration. The main controller sends a frame signal which includes a first identification code (STI) indicative of the head position of sensor data and a second identification code (STO) indicative of the head position of actuator controlling data in one frame. Each node controller including a group of sensors feeds its own sensor data to a location just behind the first identification code of the received frame signal and sends to the subsequent stage the frame signal delayed by a length of the sensor data having the received frame signal fed thereto, subsequent to the signal having the sensor data fed thereto.