Abstract: In one aspect, a data accumulation apparatus includes a script execution environment, an accumulation and retrieval unit accumulating data and performing retrieval on the accumulated data, a notification unit outputting notification in response to that data newly accumulated in the accumulation and retrieval unit matches one of conditions registered in advance, and a storage unit storing scripts and action correspondence information. The script execution environment has property of being capable of describing an instruction to perform data retrieval and an instruction to perform communication through the network, according to a script being executed.

Abstract: In one aspect, a data accumulation apparatus includes a script execution environment, an accumulation and retrieval unit accumulating data and performing retrieval on the accumulated data, a notification unit outputting notification in response to that data newly accumulated in the accumulation and retrieval unit matches one of conditions registered in advance, and a storage unit storing scripts and action correspondence information. The script execution environment has property of being capable of describing an instruction to perform data retrieval and an instruction to perform communication through the network, according to a script being executed.

Abstract: The present invention provides an electric incinerating toilet bowl and an incineration control method for the electric incinerating toilet bowl which can remove not only odor components but also smoke and soot generated when paper liners burn to thereby prevent the odor components and the smoke and soot from being exhausted. The incineration control method heats a smoke and soot removing filler layer to a smoke and soot removing temperature not lower than 350° C.

Abstract: The present invention provides an electric incinerating toilet bowl and an incineration control method for the electric incinerating toilet bowl which can remove not only odor components but also smoke and soot generated when paper liners burn to thereby prevent the odor components and the smoke and soot from being exhausted. The incineration control method heats a smoke and soot removing filler layer to a smoke and soot removing temperature not lower than 350° C.

Abstract: When bit lines or sense amplifiers are checked whether they are defective during a test performed to check whether the bit lines are defectively open, an electrical current supplied from one sense amplifier is detected by another sense amplifier. Thus, if plural bit lines are defectively open, they can be detected simultaneously. Consequently, the test time can be shortened greatly.

Abstract: When bit lines or sense amplifiers are checked whether they are defective during a test performed to check whether the bit lines are defectively open, an electrical current supplied from one sense amplifier is detected by another sense amplifier. Thus, if plural bit lines are defectively open, they can be detected simultaneously. Consequently, the test time can be shortened greatly.

Abstract: An electronic card includes a card terminal which is exposed on a surface of a card, a semiconductor integrated circuit chip including an insulated-gate field effect transistor, and a protection circuit which is provided between the card terminal and the insulated-gate field effect transistor. The protection circuit is configured to protect the insulated-gate field effect transistor from destruction against a pulse having a pulse width of 1 ns or less applied to the card terminal.

Abstract: A nonvolatile semiconductor memory device comprises, an internal memory cell array formed in internal area of a surface of semiconductor substrate, a row decoder and a column decoder formed in the internal area to select memory cell of the internal memory cell array, a peripheral circuit formed in the internal area to write and read a selected memory cell in the memory cell array, and external memory cell array formed in external area of the surface of the semiconductor substrate arranged beside the internal memory cell array and electrically separated from the internal memory cell array.

Abstract: An electronic card includes a card terminal which is exposed on a surface of a card, a semiconductor integrated circuit chip including an insulated-gate field effect transistor, and a protection circuit which is provided between the card terminal and the insulated-gate field effect transistor. The protection circuit is configured to protect the insulated-gate field effect transistor from destruction against a pulse having a pulse width of 1 ns or less applied to the card terminal.

Abstract: A semiconductor integrated circuit device includes a semiconductor region of a first conductivity type. A first insulated-gate field effect transistor having a source/drain region of a second conductivity type connected to an output terminal is formed on the semiconductor region. Further, a semiconductor region of a second conductivity type connected to the gate of the transistor is formed adjacent to the source/drain region of the transistor on the semiconductor region.

Abstract: A nonvolatile semiconductor memory device comprises, an internal memory cell array formed in internal area of a surface of semiconductor substrate, a row decoder and a column decoder formed in the internal area to select memory cell of the internal memory cell array, a peripheral circuit formed in the internal area to write and read a selected memory cell in the memory cell array, and external memory cell array formed in external area of the surface of the semiconductor substrate arranged beside the internal memory cell array and electrically separated from the internal memory cell array.

Abstract: A semiconductor integrated circuit device includes a semiconductor region of a first conductivity type. A first insulated-gate field effect transistor having a source/drain region of a second conductivity type connected to an output terminal is formed on the semiconductor region. Further, a semiconductor region of a second conductivity type connected to the gate of the transistor is formed adjacent to the source/drain region of the transistor on the semiconductor region.

Abstract: A semiconductor integrated circuit device includes a semiconductor region of a first conductivity type. A first insulated-gate field effect transistor having a source/drain region of a second conductivity type connected to an output terminal is formed on the semiconductor region. Further, a semiconductor region of a second conductivity type connected to the gate of the transistor is formed adjacent to the source/drain region of the transistor on the semiconductor region.

Abstract: A semiconductor integrated circuit device includes a semiconductor region of a first conductivity type. A first insulated-gate field effect transistor having a source/drain region of a second conductivity type connected to an output terminal is formed on the semiconductor region. Further, a semiconductor region of a second conductivity type connected to the gate of the transistor is formed adjacent to the source/drain region of the transistor on the semiconductor region.

Abstract: A non-volatile semiconductor memory device includes first, second and third comparators, counter and ring oscillator. The first comparator compares an input address with an access inhibition address. The counter counts the number of changes of addresses input after coincidence of the addresses when the first comparator detects the coincidence of the addresses. The second comparator compares the count number of the counter with a preset count number and operates the ring oscillator when the count numbers coincide with each other. The third comparator compares the cycle number of the ring oscillator with a preset cycle number and scrambles the input address to output error data when the cycle numbers coincide with each other.

Abstract: A mask ROM for storing multi-value data has a memory cell comprising a primary conductive region formed by a first conductive type semiconductor, a source region formed in the primary conductive region by a second conductive type semiconductor, a drain region formed in the primary conductive region by the second conductive type semiconductor, a channel region adjacently formed with the source region and the drain region, a gate insulation layer formed on the channel region, and a gate electrode formed on the gate insulation layer, wherein the channel region or the gate electrode is divided into a plurality of parts, each divided part having a different layer thickness from the other or a different transmissivity for ion injection, so as to form a ROM.

Abstract: A mask ROM for storing multi-value data has a memory cell comprising a primary conductive region formed by a first conductive type semiconductor, a source region formed in the primary conductive region by a second conductive type semiconductor, a drain region formed in the primary conductive region by the second conductive type semiconductor, a channel region adjacently formed with the source region and the drain region, a gate insulation layer formed on the channel region, and a gate electrode formed on the gate insulation layer, wherein the channel region or the gate electrode is divided into a plurality of parts, each divided part having a different layer thickness from the other or a different transmissivity for ion injection, so as to form a ROM.

Abstract: There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array. Each spare memory cell constituting the spare memory cell array includes a first transistor selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor connected between the interconnection between the first transistor and fuse and a ground. The fuse is selectively blown by flowing a blowing current through the fuse by selecting the second transistor through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor of the spare memory cell which is made conductive upon selection by the write line when the blowing current flows through the fuse is higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential.

Abstract: In an electrically programmable ROM, each cell 13 includes a series-connected element composed of a combination writing and reading transistor 17 and a fuse 15. One end of this series-connected element is connected to a corresponding bit line 19, and the other end thereof is grounded. A gate of the transistor 17 of the series-connected element is connected to a corresponding word line 23. Each bit line 19 is connected to a high-voltage applying pad 21 via an element such as diode or transistor provided with electrically connecting/isolating functions. When a data is written in the memory cell 13, the high-voltage applying pad 21 is electrically connected to the bit line 19. Under these conditions, if a high voltage is applied to the high-voltage applying pad 21, the transistor 17 performs snap-back action (i.e. secondary breakdown) to blow out the fuse 15. When the data is read, the high-voltage applying pad 21 is isolated from the bit line 19 without exerting influence upon the read out operation.

Abstract: A main memory cell array is divided into a plurality of blocks, and a spare memory cell group is arranged apart from the main memory cell array. The spare memory cell group uses bit lines or word lines different from those of the main memory cell array and includes spare memory cells which are different in structure from the memory cells of the main memory cell array. The number of the memory cells of the spare memory cell group is the same as that of the main memory cells of one row or column in each block of the main memory cell array, and data can be programmed into the spare memory cells after the completion of the manufacturing process. The operation of programming data into the spare memory cells of the spare memory cell array is effected by use of a write-in address buffer and a write-in decoder. When a row or column including a defective memory cell is designated in the main memory cell array, the row or column of the spare memory cells in the spare memory cell group is activated.