Abstract: Provided is an arithmetic method of performing convolution operation in convolutional layers of a neutral network by calculating matrix products. The arithmetic method includes: determining, for each of the convolutional layers, whether an amount of input data to be inputted to the convolutional layer is smaller than or equal to a predetermined amount of data; selecting a first arithmetic mode and performing convolution operation in the first arithmetic mode, when the amount of input data is determined to be smaller than or equal to the predetermined amount of data in the determining; selecting a second arithmetic mode and performing convolution operation in the second arithmetic mode, when the amount of input data is determined to be larger than the predetermined amount of data in the determining; and outputting output data which is a result obtained by performing convolution operation.

Abstract: Provided is an arithmetic method of performing convolution operation in convolutional layers of a neutral network by calculating matrix products. The arithmetic method includes: determining, for each of the convolutional layers, whether an amount of input data to be inputted to the convolutional layer is smaller than or equal to a predetermined amount of data; selecting a first arithmetic mode and performing convolution operation in the first arithmetic mode, when the amount of input data is determined to be smaller than or equal to the predetermined amount of data in the determining; selecting a second arithmetic mode and performing convolution operation in the second arithmetic mode, when the amount of input data is determined to be larger than the predetermined amount of data in the determining; and outputting output data which is a result obtained by performing convolution operation.

Abstract: Provided is a graphics rendering device that includes a frame data generation unit, access pattern setting unit, and frame data writing unit. The frame data generation unit generates, from part of stencil data, a part of frame data composed of a piece of second pixel information corresponding to a predetermined number of pixels in accordance with a first access pattern and an anti-alias pattern used in generating pieces of second pixel information. The access pattern setting unit sets, in accordance with the first access pattern and the anti-alias pattern, a second access pattern indicating pieces of second pixel information accessible by a single access to the frame buffer. The frame data writing unit writes in the frame buffer, when the frame data generation unit has generated a number of pieces of second pixel information indicated by the second access pattern, a part of the frame data corresponding to the number of pieces of second pixel information in accordance with the second access pattern.

Abstract: Provided is a graphics rendering device that includes a frame data generation unit, access pattern setting unit, and frame data writing unit. The frame data generation unit generates, from part of stencil data, a part of frame data composed of a piece of second pixel information corresponding to a predetermined number of pixels in accordance with a first access pattern and an anti-alias pattern used in generating pieces of second pixel information. The access pattern setting unit sets, in accordance with the first access pattern and the anti-alias pattern, a second access pattern indicating pieces of second pixel information accessible by a single access to the frame buffer. The frame data writing unit writes in the frame buffer, when the frame data generation unit has generated a number of pieces of second pixel information indicated by the second access pattern, a part of the frame data corresponding to the number of pieces of second pixel information in accordance with the second access pattern.

Abstract: An image generation device includes a memory in which a burst length, which is the smallest unit of read/write processing, is large; and an image generation device in which processing efficiency at the time of a memory access does not decrease, even in the case of accessing a rendering buffer for rendering a polygon. Image data is stored in a rendering buffer in block units made up of plural pixels, and image data of pixels corresponding to the polygon is stored in a serial region of the rendering buffer. A valid pixel flag indicating that a valid pixel is present within the block is stored in the rendering information buffer. The rendering buffer is accessed as little as possible based on placement of the valid pixel flags within the block.

Abstract: In an image generation device that includes a memory in which a burst length, which is the smallest unit of read/write processing, is large, an image generation device in which processing efficiency at the time of a memory access does not decrease, even in the case of accessing a rendering buffer for rendering a polygon. Image data is stored in the rendering buffer in block units made up of plural pixels. At this time, image data of pixels corresponding to the polygon is stored in a serial region of the rendering buffer. A valid pixel flag indicating that a valid pixel is present within the block is stored in a rendering information buffer. The rendering buffer is accessed as little as possible based on placement of the valid pixel flags within the block.

Abstract: A curved surface image processing apparatus 100 according to the present invention that can render an object at higher speed and in higher quality by performing image processing using NURBS data includes: a data input unit 101 for receiving NURBS data; a coordinate transformation unit 102 for performing coordinate transformation on NURBS data; an animation control unit 103 for controlling animation data of each frame to be rendered; a data transformation unit 104 for transforming NURBS data into rational Bezier data; a patch division unit 105 for subdividing a rational Bezier surface patch; a normal determination unit 106 for calculating normals of control points of a divided surface patch; a perspective transformation unit 107 for performing perspective transformation on a divided surface patch; and a rendering unit 108 for rendering a surface patch.

Abstract: The present invention provides a method of driving an active matrix display device in which one frame comprises a plurality of sub-frames each comprising a write time and a hold time and gray scale driving is brought about by the cumulative effect of the hold times. Gray scale display driving is carried out by randomly scanning scan lines other than one predetermined scan line in a predetermined sequence in the hold time of each sub-frame corresponding to the one predetermined scan line so that any one sub-frame is not written to any one scan line more than once and one frame is such that in each of the scan lines, the writings and the hold time of each of the sub-frames is ensured to bring about gray scale display. Through this means, the frame period is shortened.

Abstract: An image display device of this invention includes image memory (3) which is constructed of SRAM and which does not need any refreshing operation, image memory (3) being composed of MSB division memory (13) for storing MSB data of each pixel data item and lower-order bit division memory (14) for storing lower-order bit data other than the MSB data. In a normal mode MSB division memory (13) and lower-order bit division memory (14) are driven to cause the MSB data and the lower-order bit data to be read/written, whereas in an electric power saving mode only MSB division memory (13) is driven with lower-order bit division memory (14) remaining undriven to cause the MSB data to be read/written.

Abstract: A curved surface image processing apparatus 100 according to the present invention that can render an object at higher speed and in higher quality by performing image processing using NURBS data includes: a data input unit 101 for receiving NURBS data; a coordinate transformation unit 102 for performing coordinate transformation on NURBS data; an animation control unit 103 for controlling animation data of each frame to be rendered; a data transformation unit 104 for transforming NURBS data into rational Bezier data; a patch division unit 105 for subdividing a rational Bezier surface patch; a normal determination unit 106 for calculating normals of control points of a divided surface patch; a perspective transformation unit 107 for performing perspective transformation on a divided surface patch; and a rendering unit 108 for rendering a surface patch.

Abstract: The present invention provides a method of driving an active matrix display device in which one frame comprises a plurality of sub-frames each comprising a write time and a hold time and gray scale driving is brought about by the cumulative effect of the hold times. Gray scale display driving is carried out by randomly scanning scan lines other than one predetermined scan line in a predetermined sequence in the hold time of each sub-frame corresponding to the one predetermined scan line so that any one sub-frame is not written to any one scan line more than once and one frame is such that in each of the scan lines, the writings and the hold time of each of the sub-frames is ensured to bring about gray scale display. Through this means, the frame period is shortened.

Abstract: According to the present invention, common electrode lines each making a pair with scanning line are provided and a potential of the common electrode line is alternately changed between two predetermined values to make amplitude in potential of pixel electrode larger than that of image signals thereby decreasing the amplitude of image signals. The present invention also realizes a signal source low in price and further in power-consumption therefor, thereby realizing small-sized and low-priced liquid crystal display devices suitable for portable apparatus.

Abstract: The motion circuit of the present invention is an on-board driver circuit which is composed of polycrystal silicon semiconductor layers formed on a substrate, and which is provided with a first latch circuit for latching one of a normal phase and reverse phase clock signals having a clock skew using a clock signal and for outputting it to a shift register, and a second latch circuit for latching the other one of the normal phase and reverse phase clock signals using a clock signal and for outputting to the shift register. The latch operations of the first and second latch circuits are timed to make the two clock signals have reverse polarities. Consequently, it is realized to provide a motion circuit performing stable circuit operations without malfunctions, by preventing the occurrence of the fail phenomenon due to a skew between the normal phase and reverse phase clock signals which drive the shift register.