Patents by Inventor Malay K. Ganai

Malay K. Ganai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11755799
    Abstract: Techniques and systems for generating constrained random stimuli during functional verification of a design under verification (DUV) are described. Some embodiments can compute an observed probability distribution for each variable in a set of variables based on at least a first random solution generated using a set of constraints that are defined over the set of variables. The embodiments can then compute a correction probability distribution for each variable in the set of variables based on the observed probability distribution and an intended probability distribution. Next, while generating at least a second random solution using the set of constraints, the embodiments can select a random value for a given variable in the set of variables based on the correction probability distribution for the given variable. The observed probability distribution can be continuously updated and stored as constrained random stimuli are generated.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: September 12, 2023
    Inventor: Malay K. Ganai
  • Patent number: 8589126
    Abstract: A method for symbolic model checking for sequential systems using a combination of state-based and state-less approaches. A state-based method is used to compute frontier states by building transition relations on-the-fly using control flow information of the system, and performing successive image computations until a memory bound is reached, and efficiently storing only the new frontier states as disjunctive partitions of Boolean and Arithmetic expressions. A stateless method is used to check reachability of given goal states from a heuristically chosen set of frontier states until depth/time bound is reached. These two methods are alternated until one of the following occurs: all frontier states are explored, all goal states are reached, all computing resources are exhausted. Even though we do not store the entire reachable state set, we guarantee a complete coverage for terminating programs without the need to compute a fixed-point.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: November 19, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Malay K. Ganai, Chao Wang, Weihong Li
  • Patent number: 8538900
    Abstract: A system and method for deciding the satisfiability of a non-linear real decision problem is disclosed. Linear and non-linear constraints associated with the problem are separated. The feasibility of the linear constraints is determined using a linear solver. The feasibility of the non-linear constraints is determined using a non-linear solver which employs interval constraint propagation. The interval solutions obtained from the non-linear solver are validated using the linear solver. If the solutions cannot be validated, linear constraints are learned to refine a search space associated with the problem. The learned constraints and the non-linear constraints are iteratively solved using the non-linear solver until either a feasible solution is obtained or no solution is possible.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 17, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Malay K. Ganai, Sicun Gao, Franjo Ivancic, Aarti Gupta
  • Patent number: 8539013
    Abstract: A system and method for solving a decision problem having Boolean combinations of linear and non-linear operations includes translating the non-linear real operations using a COordinate Rotation DIgital Computer (CORDIC) method programmed on a computer device into linear operations maintaining a given accuracy. Linear and translated linear operations are combined into a formula. Satisfiability of the formula is solved using a decision procedure for Boolean combinations of linear operations over integers and reals.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: September 17, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Malay K. Ganai, Franjo Ivancic
  • Patent number: 8539451
    Abstract: Methods and systems for verifying the precision of a program that utilizes floating point operations are disclosed. Interval and affine arithmetic can be employed to build a model of the program including floating point operations and variables that are expressed as reals and integers, thereby permitting accurate determination of precision loss using a model checker. Abstract interpretation can be also employed to simplify the model. In addition, counterexample-guided abstraction refinement can be used to refine the values of parametric error constants introduced in the model.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: September 17, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Franjo Ivancic, Malay K. Ganai, Sriram Sankaranarayanan, Aarti Gupta
  • Patent number: 8532971
    Abstract: A system and method for determining satisfiability of a bounded model checking instance by restricting the decision variable ordering of the SAT solver to a sequence wherein a set of control state variables is given higher priority over the rest variables appearing in the formula. The order for control state variables is chosen based on an increasing order of the control path distance of corresponding control states from the target control state. The order of the control variables is fixed, while that of the rest is determined by the SAT search. Such a decision variable ordering strategy leads to improved performance of SAT solver by early detection and pruning of the infeasible path segments that are closer to target control state.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: September 10, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventor: Malay K. Ganai
  • Patent number: 8448145
    Abstract: Methods and systems for generating verification conditions and verifying the correctness of a concurrent system of program threads are described. The methods and systems determine and employ mutually atomic transactions to reduce verification problem sizes and state space for concurrent systems. The embodiments provide both an adequate and an optimal set of token-passing constraints for a bounded unrolling of threads.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: May 21, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Malay K. Ganai, Sudipta Kundu
  • Patent number: 8131661
    Abstract: Systems and methods are disclosed for deciding a satisfiability problem with linear and non-linear operations by: encoding non-linear integer operations into encoded linear operations with Boolean constraints by Booleaning and linearizing, combining the linear and encoded linear operations into a formula, solving the satisifiability of the formula using a solver, wherein the encoding and solving includes at least one of following: a. Booleanizing one of the non-linear operands by bit-wise structural decomposition b. Linearizing a non-linear operator by selectively choosing one of the operands for Booleanization c. Solving using an incremental lazy bounding refinement (LBR) procedure without re-encoding formula, and verifying the linear and non-linear operations in a computer software.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: March 6, 2012
    Assignee: NEC Laboratories America, Inc.
    Inventor: Malay K. Ganai
  • Publication number: 20110184705
    Abstract: A system and method for determining satisfiability of a bounded model checking instance by restricting the decision variable ordering of the SAT solver to a sequence wherein a set of control state variables is given higher priority over the rest variables appearing in the formula. The order for control state variables is chosen based on an increasing order of the control path distance of corresponding control states from the target control state. The order of the control variables is fixed, while that of the rest is determined by the SAT search. Such a decision variable ordering strategy leads to improved performance of SAT solver by early detection and pruning of the infeasible path segments that are closer to target control state.
    Type: Application
    Filed: August 31, 2010
    Publication date: July 28, 2011
    Applicant: NEC Laboratories America, Inc.
    Inventor: MALAY K. GANAI
  • Publication number: 20110173148
    Abstract: A system and method for deciding the satisfiability of a non-linear real decision problem is disclosed. Linear and non-linear constraints associated with the problem are separated. The feasibility of the linear constraints is determined using a linear solver. The feasibility of the non-linear constraints is determined using a non-linear solver which employs interval constraint propagation. The interval solutions obtained from the non-linear solver are validated using the linear solver. If the solutions cannot be validated, linear constraints are learned to refine a search space associated with the problem. The learned constraints and the non-linear constraints are iteratively solved using the non-linear solver until either a feasible solution is obtained or no solution is possible.
    Type: Application
    Filed: December 13, 2010
    Publication date: July 14, 2011
    Applicant: NEC Laboratories America, Inc.
    Inventors: MALAY K. GANAI, Sicun Gao, Franjo Ivancic, Aarti Gupta
  • Patent number: 7949511
    Abstract: A system and method for bounded model checking of computer programs includes providing a program having at least one reachable property node. The program is decomposed for bounded model checking (BMC) into subproblems by creating a tunnel based on disjunctive control paths through the program. A reduced BMC sub-problem obtained using BMC unrolling, while using path constraints imposed by the at least one tunnel. For the reachable property node, determining a quantifier-free formula (QFP) in a decidable subset of first order logic. Satisfiability of the QFP is checked, independently and individually, to determine whether the QFP is satisfiable for the subproblem. The decomposing is continued until the a BMC bound is reached.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: May 24, 2011
    Assignee: NEC Laboratories America, Inc.
    Inventor: Malay K. Ganai
  • Publication number: 20100305919
    Abstract: A method for symbolic model checking for sequential systems using a combination of state-based and state-less approaches. A state-based method is used to compute frontier states by building transition relations on-the-fly using control flow information of the system, and performing successive image computations until a memory bound is reached, and efficiently storing only the new frontier states as disjunctive partitions of Boolean and Arithmetic expressions. A stateless method is used to check reachability of given goal states from a heuristically chosen set of frontier states until depth/time bound is reached. These two methods are alternated until one of the following occurs: all frontier states are explored, all goal states are reached, all computing resources are exhausted. Even though we do not store the entire reachable state set, we guarantee a complete coverage for terminating programs without the need to compute a fixed-point.
    Type: Application
    Filed: April 2, 2010
    Publication date: December 2, 2010
    Applicant: NEC Laboratories America, Inc.
    Inventors: MALAY K. GANAI, Chao Wang, Weihong Li
  • Publication number: 20100293530
    Abstract: Methods and systems for verifying the precision of a program that utilizes floating point operations are disclosed. Interval and affine arithmetic can be employed to build a model of the program including floating point operations and variables that are expressed as reals and integers, thereby permitting accurate determination of precision loss using a model checker. Abstract interpretation can be also employed to simplify the model. In addition, counterexample-guided abstraction refinement can be used to refine the values of parametric error constants introduced in the model.
    Type: Application
    Filed: April 16, 2010
    Publication date: November 18, 2010
    Applicant: NEC Laboratories America, Inc.
    Inventors: FRANJO IVANCIC, Malay K. Ganai, Sriram Sankaranarayanan, Aarti Gupta
  • Publication number: 20100281086
    Abstract: A system and method for solving a decision problem having Boolean combinations of linear and non-linear operations includes translating the non-linear real operations using a COordinate Rotation DIgital Computer (CORDIC) method programmed on a computer device into linear operations maintaining a given accuracy. Linear and translated linear operations are combined into a formula. Satisfiablity of the formula is solved using a decision procedure for Boolean combinations of linear operations over integers and reals.
    Type: Application
    Filed: February 22, 2010
    Publication date: November 4, 2010
    Applicant: NEC Laboratories America, Inc.
    Inventors: MALAY K. GANAI, Franjo Ivancic
  • Publication number: 20100088680
    Abstract: Methods and systems for generating verification conditions and verifying the correctness of a concurrent system of program threads are described. The methods and systems determine and employ mutually atomic transactions to reduce verification problem sizes and state space for concurrent systems. The embodiments provide both an adequate and an optimal set of token-passing constraints for a bounded unrolling of threads.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 8, 2010
    Applicant: NEC Laboratories America, Inc.
    Inventors: MALAY K. GANAI, Sudipta Kundu
  • Publication number: 20090292941
    Abstract: Systems and methods are disclosed for performing error diagnosis of software errors in a program by from one or more error traces, building a repair program containing one or more modified program semantics corresponding to fixes to observed errors; encoding the repair program with constraints, biases and priortization into a constraint weighted problem; and solving the constraint weighted problem to generate one or more repair solutions, wherein the encoding includes at least one of: a) constraining one or more repairs choices guided by automatically inferring one or more partial specifications of intended program behaviors and program structure; b) biasing one or more repair choices guided by typical programming mistakes; and c) prioritizing the repair solutions based on error locations and possible changes in program semantics.
    Type: Application
    Filed: December 9, 2008
    Publication date: November 26, 2009
    Applicant: NEC LABORATORIES AMERICA, INC.
    Inventors: Malay K. Ganai, Gogul Balakrishnan
  • Publication number: 20090222393
    Abstract: Systems and methods are disclosed for deciding a satisfiability problem with linear and non-linear operations by: encoding non-linear integer operations into encoded linear operations with Boolean constraints by Booleaning and linearizing, combining the linear and encoded linear operations into a formula, solving the satisifiability of the formula using a solver, wherein the encoding and solving includes at least one of following: a. Booleanizing one of the non-linear operands by bit-wise structural decomposition b. Linearizing a non-linear operator by selectively choosing one of the operands for Booleanization c. Solving using an incremental lazy bounding refinement (LBR) procedure without re-encoding formula, and verifying the linear and non-linear operations in a computer software.
    Type: Application
    Filed: December 9, 2008
    Publication date: September 3, 2009
    Applicant: NEC LABORATORIES AMERICA, INC.
    Inventor: Malay K. Ganai
  • Publication number: 20090132991
    Abstract: A system and method for program testing includes, using a static analysis, determining dependency relations of enabled running processes in a program. The dependency relations are organized in a matrix to provide an interface for exploring the program. A reduced set of possible executions obtained by removal of redundant interleavings as determined with respect to the dependency relation, is explored on the program in a stateless exploration process that analyzes executed states and transitions to verify operation of the program.
    Type: Application
    Filed: November 5, 2008
    Publication date: May 21, 2009
    Applicant: NEC Laboratories America, Inc
    Inventors: Malay K. Ganai, Sudipta Kundu
  • Publication number: 20090125294
    Abstract: A system and method for bounded model checking of computer programs includes providing a program having at least one reachable property node. The program is decomposed for bounded model checking (BMC) into subproblems by creating a tunnel based on disjunctive control paths through the program. A reduced BMC sub-problem obtained using BMC unrolling, while using path constraints imposed by the at least one tunnel. For the reachable property node, determining a quantifier-free formula (QFP) in a decidable subset of first order logic. Satisfiability of the QFP is checked, independently and individually, to determine whether the QFP is satisfiable for the subproblem. The decomposing is continued until the a BMC bound is reached.
    Type: Application
    Filed: July 31, 2008
    Publication date: May 14, 2009
    Applicant: NEC LABORATORIES AMERICA, INC.
    Inventor: Malay K. Ganai
  • Patent number: 7305637
    Abstract: An efficient approach for SAT-based quantifier elimination and pre-image computation using unrolled designs that significantly improves the performance of pre-image and fix-point computation in SAT-based unbounded symbolic model checking.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: December 4, 2007
    Assignee: NEC Laboratories America, Inc.
    Inventors: Malay K. Ganai, Aarti Gupta, Pranav Ashar