Abstract: Chemical mechanical polishing (CMP) compositions, methods and systems for polish cobalt or cobalt-containing substrates are provided. The CMP compositions comprise ?-alanine, abrasive particles, a salt of phosphate, corrosion inhibitor, oxidizer and water. The cobalt chemical mechanical polishing compositions provide high removal rate of Co as well as very high selectivity of Co film vs. dielectric film, such as TEOS, SixNy (with 1.0<x<3.0, 1.33<y<4.0), low-k, and ultra low-k films.

Abstract: Chemical Mechanical Planarization (CMP) polishing compositions comprising composite particles, such as ceria coated silica particles, offer low dishing, low defects, and high removal rate for polishing oxide films. Chemical Mechanical Planarization (CMP) polishing compositions have shown excellent performance using soft polishing pad.

Abstract: Chemical Mechanical Planarization (CMP) polishing compositions comprising composite particles, such as ceria coated silica particles, offer low dishing, low defects, and high removal rate for polishing oxide films. Chemical Mechanical Planarization (CMP) polishing compositions have shown excellent performance using soft polishing pad.

Abstract: Chemical Mechanical Planarization (CMP) polishing compositions comprising composite particles, such as ceria coated silica particles, offer low dishing, low defects, and high removal rate for polishing oxide films. Chemical Mechanical Planarization (CMP) polishing compositions have shown excellent performance using soft polishing pad.

Abstract: Copper chemical mechanical polishing (CMP) formulation, method and system are disclosed. The CMP formulation comprises particulate materials, at least two or more amino acids, oxidizer, corrosion inhibitor, and rest being water.

Abstract: Chemical mechanical polishing (CMP) compositions, methods and systems for polish cobalt or cobalt-containing substrates are provided. The CMP compositions comprise ?-alanine, abrasive particles, a salt of phosphate, corrosion inhibitor, oxidizer and water. The cobalt chemical mechanical polishing compositions provide high removal rate of Co as well as very high selectivity of Co film vs. dielectric film, such as TEOS, SixNy (with 1.0<x<3.0, 1.33<y<4.0), low-k, and ultra low-k films.

Abstract: Copper chemical mechanical polishing (CMP) formulation, method and system are disclosed. The CMP formulation comprises particulate materials, at least two or more amino acids, oxidizer, corrosion inhibitor, and rest being water.

Abstract: Chemical Mechanical Planarization (CMP) polishing compositions comprising composite particles, such as ceria coated silica particles, offer low dishing, low defects, and high removal rate for polishing oxide films. Chemical Mechanical Planarization (CMP) polishing compositions have shown excellent performance using soft polishing pad.

Abstract: Slurries and associated methods and systems for the chemical mechanical planarization (CMP) of tungsten-containing films on semiconductor wafers are described. The slurries comprise abrasive particles, activator-containing particles, peroxygen oxidizer, pH adjustor, and the remaining being water. The slurries have a pH in the range of 4 to 10; preferably 5 to 9; more preferably 6 to 8.

Abstract: An engagement probe for engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: An exemplary engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate is described. Constructions are disclosed for testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: The invention is a method and apparatus for planarizing a wafer. Discrete measurements are taken across the surface of the wafer at a desired spatial density. The measurements may be generated using a flash lamp to reflect a light signal off the surface of the wafer with a spectrometer analyzing the reflected light. A plurality of probes may be used at different locations to shorten the time necessary for taking measurements across the full front surface of the wafer and for allowing a plurality of areas to be sampled substantially simultaneously. A control system receives the measurements and their corresponding locations. The control system is then able to analyze the data looking for areas or bands on the front surface of the wafer that need an increase or decrease in material removal rate. The control system is then able to adjust one or more planarization parameters to improve the process for the current wafer or for future wafers.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conducive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: The invention is a method and apparatus for planarizing a wafer. Discrete measurements are taken across the surface of the wafer at a desired spatial density. The measurements may be generated using a flash lamp to reflect a light signal off the surface of the wafer with a spectrometer analyzing the reflected light. A plurality of probes may be used at different locations to shorten the time necessary for taking measurements across the full front surface of the wafer and for allowing a plurality of areas to be sampled substantially simultaneously. A control system receives the measurements and their corresponding locations. The control system is then able to analyze the data looking for areas or bands on the front surface of the wafer that need an increase or decrease in material removal rate. The control system is then able to adjust one or more planarization parameters to improve the process for the current wafer or for future wafers.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: The invention is a method and apparatus for planarizing a wafer. Discrete measurements are taken across the surface of the wafer at a desired spatial density. The measurements may be generated using a flash lamp to reflect a light signal off the surface of the wafer with a spectrometer analyzing the reflected light. A plurality of probes may be used at different locations to shorten the time necessary for taking measurements across the full front surface of the wafer and for allowing a plurality of areas to be sampled substantially simultaneously. A control system receives the measurements and their corresponding locations. The control system is then able to analyze the data looking for areas or bands on the front surface of the wafer that need an increase or decrease in material removal rate. The control system is then able to adjust one or more planarization parameters to improve the process for the current wafer or for future wafers.