Patents by Inventor Malcolm J. Wing
Malcolm J. Wing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8824468Abstract: A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.Type: GrantFiled: September 6, 2011Date of Patent: September 2, 2014Assignee: Agate Logic, Inc.Inventors: Malcolm J. Wing, Jay B. Patel, Jeffrey M. Schroeder
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Patent number: 8719544Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.Type: GrantFiled: September 23, 2011Date of Patent: May 6, 2014Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
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Patent number: 8405418Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.Type: GrantFiled: May 14, 2011Date of Patent: March 26, 2013Assignee: Agate Logic, Inc.Inventors: Dana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
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Publication number: 20120110306Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.Type: ApplicationFiled: September 23, 2011Publication date: May 3, 2012Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
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Publication number: 20110317720Abstract: A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.Type: ApplicationFiled: September 6, 2011Publication date: December 29, 2011Applicant: Agate Logic, Inc.Inventors: Malcolm J. Wing, Jay B. Patel, Jeffrey M. Schroeder
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Patent number: 8055877Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.Type: GrantFiled: October 11, 2005Date of Patent: November 8, 2011Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
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Patent number: 8050262Abstract: A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.Type: GrantFiled: July 5, 2010Date of Patent: November 1, 2011Assignee: Agate Logic, IncInventors: Malcolm J. Wing, Jay B. Patel, Jeffrey M. Schroeder
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Patent number: 7944236Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.Type: GrantFiled: August 12, 2010Date of Patent: May 17, 2011Assignee: Agate Logic, Inc.Inventors: Dana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
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Patent number: 7902862Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.Type: GrantFiled: September 14, 2007Date of Patent: March 8, 2011Assignee: Agate Logic, Inc.Inventors: Dana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
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Publication number: 20100329262Abstract: A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.Type: ApplicationFiled: July 5, 2010Publication date: December 30, 2010Inventors: Malcolm J. Wing, Jay B. Patel, Jeffrey M. Schroeder
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Publication number: 20100306429Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.Type: ApplicationFiled: August 12, 2010Publication date: December 2, 2010Applicant: AGATE LOGIC, INC.Inventors: Dana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
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Patent number: 7840776Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.Type: GrantFiled: October 30, 2000Date of Patent: November 23, 2010Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
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Publication number: 20100205413Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.Type: ApplicationFiled: April 16, 2010Publication date: August 12, 2010Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
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Patent number: 7773595Abstract: A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.Type: GrantFiled: September 14, 2007Date of Patent: August 10, 2010Assignee: Agate Logic, Inc.Inventors: Malcolm J. Wing, Jay B. Patel, Jeffrey M. Schroeder
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Patent number: 7716452Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.Type: GrantFiled: May 13, 2003Date of Patent: May 11, 2010Inventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing
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Patent number: 7557605Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.Type: GrantFiled: September 14, 2007Date of Patent: July 7, 2009Assignee: Cswitch CorporationInventors: Godfrey P. D'Souza, Douglas Laird, Malcolm J. Wing, Colin N. Murphy, Dana L. How, Robert Yu, Jay B. Patel, Ivo Dobbelaere, Jason Golbus, Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Dave Trossen, Kevin James
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Publication number: 20090072858Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.Type: ApplicationFiled: September 14, 2007Publication date: March 19, 2009Applicant: CSWITCH CORPORATIONInventors: Godfrey P. D'Souza, Douglas Laird, Malcolm J. Wing, Colin N. Murphy, Dana L. How, Robert Yu, Jay B. Patel, Ivo Dobbelaere, Jason Golbus, Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Dave Trossen, Kevin James
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Publication number: 20090073970Abstract: A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit.Type: ApplicationFiled: September 14, 2007Publication date: March 19, 2009Applicant: CSWITCH CORPORATIONInventors: Malcolm J. Wing, Jay B. Patel, Jeffrey M. Schroeder
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Publication number: 20090073967Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.Type: ApplicationFiled: September 14, 2007Publication date: March 19, 2009Inventors: Dana How, Godfrey P. D'Souza, Malcolm J. Wing, Colin N. Murphy, Arun Jangity
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Patent number: 6199152Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.Type: GrantFiled: August 22, 1996Date of Patent: March 6, 2001Assignee: Transmeta CorporationInventors: Edmund J. Kelly, Robert F. Cmelik, Malcolm J. Wing