Patents by Inventor Malgorzata Jurczak
Malgorzata Jurczak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10256403Abstract: The present disclosure relates generally to Hf-comprising materials for use in, for example, the insulator of a RRAM device, and to methods for making such materials. In one aspect, the disclosure provides a method for the manufacture of a layer of material over a substrate, said method including a) providing a substrate, and b) depositing a layer of material on said substrate via ALD at a temperature of from 250 to 500° C., said depositing step comprising: at least one HfX4 pulse, and at least one trimethyl-aluminum (TMA) pulse, wherein X is a halogen selected from Cl, Br, I and F and is preferably Cl.Type: GrantFiled: July 27, 2016Date of Patent: April 9, 2019Assignee: IMECInventors: Christoph Adelmann, Malgorzata Jurczak
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Patent number: 9786795Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory devices having a resistance switching element, particularly resistive random access memory (RRAM) devices. In one aspect, a selector device includes a first barrier structure comprising a first metal and a first semiconductor or a first low bandgap dielectric material, and a second barrier structure comprising a second metal and a second semiconductor or a second low bandgap dielectric material. The selector device additionally includes an insulator interposed between the first semiconductor or the first low bandgap dielectric material and the second semiconductor or the second low bandgap dielectric material. The first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure.Type: GrantFiled: October 7, 2014Date of Patent: October 10, 2017Assignees: IMEC VZW, Katholieke Universiteit LeuvenInventors: Bogdan Govoreanu, Christoph Adelmann, Leqi Zhang, Malgorzata Jurczak
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Publication number: 20160336511Abstract: The present disclosure relates generally to Hf-comprising materials for use in, for example, the insulator of a RRAM device, and to methods for making such materials. In one aspect, the disclosure provides a method for the manufacture of a layer of material over a substrate, said method including a) providing a substrate, and b) depositing a layer of material on said substrate via ALD at a temperature of from 250 to 500° C., said depositing step comprising: at least one HfX4 pulse, and at least one trimethyl-aluminum (TMA) pulse, wherein X is a halogen selected from Cl, Br, I and F and is preferably Cl.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Applicant: IMECInventors: Christoph Adelmann, Malgorzata Jurczak
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Patent number: 9437817Abstract: The present disclosure relates generally to Hf-comprising materials for use in, for example, the insulator of a RRAM device, and to methods for making such materials. In one aspect, the disclosure provides a method for the manufacture of a layer of material over a substrate, said method including a) providing a substrate, and b) depositing a layer of material on said substrate via ALD at a temperature of from 250 to 500° C., said depositing step comprising: at least one HfX4 pulse, and at least one trimethyl-aluminum (TMA) pulse, wherein X is a halogen selected from Cl, Br, I and F and is preferably Cl.Type: GrantFiled: August 5, 2013Date of Patent: September 6, 2016Assignee: IMECInventors: Christoph Adelmann, Malgorzata Jurczak
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Publication number: 20150097187Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory devices having a resistance switching element, particularly resistive random access memory (RRAM) devices. In one aspect, a selector device includes a first barrier structure comprising a first metal and a first semiconductor or a first low bandgap dielectric material, and a second barrier structure comprising a second metal and a second semiconductor or a second low bandgap dielectric material. The selector device additionally includes an insulator interposed between the first semiconductor or the first low bandgap dielectric material and the second semiconductor or the second low bandgap dielectric material. The first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure.Type: ApplicationFiled: October 7, 2014Publication date: April 9, 2015Inventors: Bogdan GOVOREANU, Christoph ADELMANN, Leqi ZHANG, Malgorzata JURCZAK
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Publication number: 20140034894Abstract: The present disclosure relates generally to Hf-comprising materials for use in, for example, the insulator of a RRAM device, and to methods for making such materials. In one aspect, the disclosure provides a method for the manufacture of a layer of material over a substrate, said method including a) providing a substrate, and b) depositing a layer of material on said substrate via ALD at a temperature of from 250 to 500° C., said depositing step comprising: at least one HfX4 pulse, and at least one trimethyl-aluminum (TMA) pulse, wherein X is a halogen selected from Cl, Br, I and F and is preferably Cl.Type: ApplicationFiled: August 5, 2013Publication date: February 6, 2014Applicant: IMECInventors: Christoph Adelmann, Malgorzata Jurczak
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Patent number: 8391059Abstract: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.Type: GrantFiled: June 24, 2011Date of Patent: March 5, 2013Assignee: IMECInventors: Zhichao Lu, Nadine Collaert, Marc Aoulaiche, Malgorzata Jurczak
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Publication number: 20110317486Abstract: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.Type: ApplicationFiled: June 24, 2011Publication date: December 29, 2011Applicant: IMECInventors: Zhichao Lu, Nadine Collaert, Marc Aoulaiche, Malgorzata Jurczak
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Patent number: 7494902Abstract: A method is disclosed for relaxing strain in a multi-gate device, the method comprising providing a substrate with a strained material, patterning a plurality of fins in the strained material, defining a first region comprising at least one fin, defining a second region comprising at least one fin, providing a diffusion barrier layer on the first region, performing a hydrogen anneal such that the strain in the second region is relaxed.Type: GrantFiled: June 22, 2007Date of Patent: February 24, 2009Assignee: Interuniversitair Microelektronica Centrum vzw (IMEC)Inventors: Malgorzata Jurczak, Rita Rooyackers, Nadine Collaert
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Patent number: 7396736Abstract: A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.Type: GrantFiled: August 29, 2005Date of Patent: July 8, 2008Assignee: STMicroelectronics SAInventors: Hervé Jaouen, Thomas Skotnicki, Malgorzata Jurczak
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Publication number: 20070298549Abstract: A method is disclosed for relaxing strain in a multi-gate device, the method comprising providing a substrate with a strained material, patterning a plurality of fins in the strained material, defining a first region comprising at least one fin, defining a second region comprising at least one fin, providing a diffusion barrier layer on the first region, performing a hydrogen anneal such that the strain in the second region is relaxed.Type: ApplicationFiled: June 22, 2007Publication date: December 27, 2007Applicant: Interuniversitair Microelektronica Centrum vzw (IMEC)Inventors: Malgorzata Jurczak, Rita Rooyackers, Nadine Collaert
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Patent number: 7224015Abstract: The invention concerns a method which consists in forming on a substrate (1) coated with a dielectric material layer (3) provided with a window (3a), a stack of successive layers alternately of germanium or SiGe alloy (4, 6, 8) and polycrystalline silicon (5, 7, 9); selective partial elimination of the germanium or SiGe alloy layers, to form an tree-like structure; forming a thin layer of dielectric material (10) on the tree-like structure; and coating the tree-like structure with polycrystalline silicon (11). The invention is useful for making dynamic random-access memories.Type: GrantFiled: November 10, 2000Date of Patent: May 29, 2007Assignee: STMicroelectronics SAInventors: Thomas Skotnicki, Malgorzata Jurczak, Catherine Mallardeau
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Patent number: 7038285Abstract: A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.Type: GrantFiled: December 6, 2000Date of Patent: May 2, 2006Assignee: STMicroelectronics SAInventors: Hervé Jaouen, Thomas Skotnicki, Malgorzata Jurczak
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Publication number: 20060001113Abstract: A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.Type: ApplicationFiled: August 29, 2005Publication date: January 5, 2006Applicant: STMicroelectronics SAInventors: Herve Jaouen, Thomas Skotnicki, Malgorzata Jurczak
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Patent number: 6855605Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.Type: GrantFiled: October 30, 2002Date of Patent: February 15, 2005Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Malgorzata Jurczak, Rita Rooyackers, Emmanuel Augendre, Goncal Badenes
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Patent number: 6727186Abstract: A method of fabricating an SON structure semiconductor device is described. There is formed, on a silicon substrate, a stack of layers comprising first and second successive combinations. Each successive combination has a bottom silicon-germanium alloy (Site) layer and a top silicon layer. In a conventional way, a gate dielectric layer, a gate, spacers, source and drain regions, and an external passivating layer are formed by ionic implantation. A vertical hole is formed in the gate as far as the bottom Site layer to etch a part of the Site layers to form tunnels. The walls of the hole and the tunnels are then internally passivated so that the tunnels can remain empty or be filled.Type: GrantFiled: April 15, 2002Date of Patent: April 27, 2004Assignee: France TélécomInventors: Thomas Skotnicki, Malgorzata Jurczak
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Patent number: 6713356Abstract: A method of fabricating a semiconductor device consisting of a silicon substrate on which is formed a stack of layers is described. The stack may have successively at least one first and one second combination. Each combination may consist, with reference to the substrate, of a thin bottom SiGe layer and a thin top silicon layer. A thin silicon dioxide film (18) is formed on the thin top silicon layer of the second combination so that the layer concerned supports the layers of the stack on at least two opposite lateral sides of the stack. Successive selective lateral etching of the SiGe layers is then carried out to form tunnels which are filled with a dielectric material.Type: GrantFiled: April 23, 2002Date of Patent: March 30, 2004Assignee: France TélécomInventors: Thomas Skotnicki, Malgorzata Jurczak
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Patent number: 6670686Abstract: A transmitter or receiver includes several transducers formed opposite an aperture in a package. Each transducer includes a deformable semiconductor membrane that is capable of conducting current. The membrane is separated from a substrate zone by a cavity. This allows the membrane to deform due to the effect of an acoustic pressure or of a Lorenz force.Type: GrantFiled: September 16, 2002Date of Patent: December 30, 2003Assignee: STMicroelectronics SAInventors: Hervé Jaouen, Thomas Skotnicki, Malgorzata Jurczak
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Patent number: 6607968Abstract: A method for making a silicon substrate having a buried thin silicon oxide film is described. The method consists of: a) producing a first element having a first silicon body whereof the main surface is coated, in succession, with a buffer layer of germanium, or of an alloy of germanium and silicon, and with a thin silicon film; b) producing a second element, having a silicon body whereof a main surface is coated with a thin silicon oxide film; c) linking the first element with the second element such that the thin silicon film of the first element is in contact with the thin silicon oxide film of the second element; and d) eliminating the buffer layer to recuperate the silicon substrate having a buried thin silicon oxide film and a reusable silicon substrate. The method may be useful in making microelectronic devices such as CMOS and MOSFET devices.Type: GrantFiled: April 22, 2002Date of Patent: August 19, 2003Assignee: France TelecomInventors: Malgorzata Jurczak, Thomas Skotnicki
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Patent number: RE41841Abstract: A method for making a silicon substrate having a buried thin silicon oxide film is described. The method consists of: a) producing a first element having a first silicon body whereof the main surface is coated, in succession, with a buffer layer of germanium, or of an alloy of germanium and silicon, and with a thin silicon film; b) producing a second element, having a silicon body whereof a main surface is coated with a thin silicon oxide film; c) linking the first element with the second element such that the thin silicon film of the first element is in contact with the thin silicon oxide film of the second element; and d) eliminating the buffer layer to recuperate the silicon substrate having a buried thin silicon oxide film and a reusable silicon substrate. The method may be useful in making microelectronic devices such as CMOS and MOSFET devices.Type: GrantFiled: June 8, 2000Date of Patent: October 19, 2010Inventors: Malgorzata Jurczak, Thomas Skotnicki