Abstract: The present invention is directed to a line address computer for calculating the starting line addresses for lines of a decoded frame. The starting addresses for a display frame are provided to the line address computer by a host processor. The line address computer determines the starting line addresses for subsequent lines by appropriately incrementing the line addresses of previous lines.

Abstract: Presented herein are video decoding system(s), method(s), and apparatus for repeating a last line to a scalar or compositor or capture. A first parameter is provided to a first register indicating that a picture comprises a first number of lines, and a second parameter is provided to a second register, indicating that the picture comprises a second number of lines.

Abstract: Presented herein are systems and methods for clock rate determination. A bitstream is sampled by sampling a transmitted clock signal at a rate corresponding to a receiver clock signal, and measuring an average number of consecutive samples that have a same state selected from a first state and a second state.

Abstract: Presented herein are systems and methods for pixel reordering and selection. A decoded frame is stored in a frame buffer with a particular pixel order and byte order. A pixel feeder fetches portions of the decoded frame and stores portions of the frame in a double buffer with the same pixel order and byte order. An endian swizzle converts the byte ordering to a predetermined format, as needed. Reordering logic changes the pixel order to a predetermined order. Selection logic selects luma and chroma pixels from fetched pixels and provides the luma pixels to a luma pixel register, chroma Cr pixels to a chroma Cr pixel register, and chroma Cb pixels to a chroma Cb pixel register.

Abstract: Presented herein is a system and method for a line address computer for providing line addresses in multiple contexts for interlaced to progressive conversion. A feeder fetches a first line from a top field, fetches a first line from a bottom field corresponding to the top field, after fetching the first line from the top field, and fetches a second line from the top field after fetching the first line from the bottom field. The second line from the top field is adjacent to the first line in the top field.

Abstract: Presented herein is a line address computer for providing chroma coefficients to a chroma filter. At each horizontal synchronization pulse, the line address computer provides a set of interpolation weights to a chroma filter. The chroma filter uses the provided set of weights to interpolate pixels in chroma pixel positions in a display format from chroma pixels in another format.

Abstract: Presented herein are systems and methods for clock rate determination. A bitstream is sampled by sampling a transmitted clock signal at a rate corresponding to a receiver clock signal, and measuring an average number of consecutive samples that have a same state selected from a first state and a second state.

Abstract: Presented herein are video decoding system(s), method(s), and apparatus for repeating a last line to a scalar or compositor or capture. A first parameter is provided to a first register indicating that a picture comprises a first number of lines, and a second parameter is provided to a second register, indicating that the picture comprises a second number of lines.

Abstract: Presented herein is a dual context audio parser. A header of the audio frame is provided for parsing, the header forming a portion of a particular packet. A first portion of the audio frame is provided for parsing, the first portion of the audio frames being stored in a memory. A second portion of the audio frame is provided for parsing, the second portion of the audio frame forming another portion of the particular packet, after the first portion is parsed.

Abstract: Presented herein are systems and methods for repeating a last picture. A first frame is provided for display a first time. After displaying the first frame, the information about a second frame to display is awaited. The first frame is repeated if the information regarding the second frame is not received before a predetermined time.

Abstract: Presented herein is a system and method for a line address computer for providing line addresses in multiple contexts for interlaced to progressive conversion. A feeder fetches a first line from a top field, fetches a first line from a bottom field corresponding to the top field, after fetching the first line from the top field, and fetches a second line from the top field after fetching the first line from the bottom field. The second line from the top field is adjacent to the first line in the top field.

Abstract: Presented herein are systems and methods for pixel reordering and selection. A decoded picture is stored in a frame buffer with a particular pixel order and byte order. A input data write unit fetches portions of the decoded picture and stores portions of the picture in a double buffer with the same pixel order and byte order. An endian swizzle converts the byte ordering to a predetermined format, as needed. Reordering logic changes the pixel order to a predetermined order. Selection logic selects luma and chroma pixels from fetched pixels and provides the luma pixels to a luma pixel register, chroma Cr pixels to a chroma Cr pixel register, and chroma Cb pixels to a chroma Cb pixel register.

Abstract: Presented herein is a line address computer for providing chroma coefficients to a chroma filter. At each horizontal synchronization pulse, the line address computer provides a set of interpolation weights to a chroma filter. The chroma filter uses the provided set of weights to interpolate pixels in chroma pixel positions in a display format from chroma pixels in another format.

Abstract: The present invention is directed to a line address computer for calculating the starting line addresses for lines of a decoded frame. The starting addresses for a display frame are provided to the line address computer by a host processor. The line address computer determines the starting line addresses for subsequent lines by appropriately incrementing the line addresses of previous lines.

Abstract: Presented herein are systems and methods for pixel reordering and selection. A decoded frame is stored in a frame buffer with a particular pixel order and byte order. A pixel feeder fetches portions of the decoded frame and stores portions of the frame in a double buffer with the same pixel order and byte order. An endian swizzle converts the byte ordering to a predetermined format, as needed. Reordering logic changes the pixel order to a predetermined order. Selection logic selects luma and chroma pixels from fetched pixels and provides the luma pixels to a luma pixel register, chroma Cr pixels to a chroma Cr pixel register, and chroma Cb pixels to a chroma Cb pixel register.