Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor memory device includes a plurality of memory chips that are stacked above one another and connected to each other through a through via, an interface chip that is connected to the plurality of memory chips, and a plurality of first terminals for connection with an external device. The interface chip includes a plurality of second terminals that are connected to the plurality of first terminals, and is capable of receiving a signal that is supplied from the external device through the first and second terminals, and stores configuration information according to which a set number of the second terminals are designated for receiving control signals for the plurality of memory chips.

Abstract: A semiconductor memory device includes a plurality of memory chips that are stacked above one another and connected to each other through a through via, an interface chip that is connected to the plurality of memory chips, and a plurality of first terminals for connection with an external device. The interface chip includes a plurality of second terminals that are connected to the plurality of first terminals, and is capable of receiving a signal that is supplied from the external device through the first and second terminals, and stores configuration information according to which a set number of the second terminals are designated for receiving control signals for the plurality of memory chips.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked first chips and a second chip. The second chip outputs a first signal to the first chips. The first chip outputs status information at timing based on the received first signal. The first chip shifts the received first signal and outputs the shifted first signal to the first chip of a next stage in synchronization with the first clock signal. The second chip receives a plurality of status information output in a serial manner from the first chips.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked first chips and a second chip. The second chip outputs a first signal to the first chips. The first chip outputs status information at timing based on the received first signal. The first chip shifts the received first signal and outputs the shifted first signal to the first chip of a next stage in synchronization with the first clock signal. The second chip receives a plurality of status information output in a serial manner from the first chips.

Abstract: A semiconductor storage device according to an embodiment includes multiple memory cells which electrically rewrite data, a well control circuit which outputs an erasure voltage to be applied to a well through an output terminal, a first pump circuit which outputs a voltage set by boosting an input voltage to the output terminal, a second pump circuit which outputs a voltage set by boosting the input voltage to the output terminal and outputs a voltage higher than an output voltage of the first pump circuit, a pump switching detecting circuit which outputs an assist signal to perform a boosting operation on at least one of the first pump circuit and the second pump circuit and an erase pulse control circuit which sets target voltages of the first pump circuit and the second pump circuit, on the basis of setting values to set a target voltage of the erasure voltage.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a first memory block and a second memory block, and a control circuit. In read operation, when a read target block is the first memory block, the control circuit determines whether the first memory block is single-level or multi-level according to a first flag, and stores a first determination result thereof. While the read target block is the first memory block, the control circuit reads the first memory block as single-level or multi-level according to the first determination result. When the read target block is changed from the first memory block to the second memory block, the control circuit erases the first determination result.

Abstract: A semiconductor storage device according to an embodiment includes a plurality of memory cells which electrically rewrite data by controlling the amount of charges accumulated in a floating gate formed on a well through a tunnel insulating film. The semiconductor storage device includes a well control circuit which outputs an erasure voltage to be applied to the well through an output terminal. The semiconductor storage device includes a first pump circuit which outputs a voltage set by boosting an input voltage to the output terminal. The semiconductor storage device includes a second pump circuit which outputs a voltage set by boosting the input voltage to the output terminal and outputs a voltage higher than an output voltage of the first pump circuit. The semiconductor storage device includes a pump switching detecting circuit which outputs an assist signal to perform a boosting operation on at least one of the first pump circuit and the second pump circuit.