Abstract: In an analog-digital mixed master for a Bi-CMOS analog/digital mixed LSI, an analog circuit and a digital circuit are interconnected through selectors, which are also connected to test terminals and which are controlled by test mode terminals. By changing the signals applied to the test mode terminals, the analog circuit and the digital circuit are interconnected through the selectors, or the analog circuit is connected through the selectors to the test terminals, or the digital circuit is connected through the selectors to the test terminals. Thus, the analog circuit and the digital circuit can be tested independently of each other.

Abstract: An analog/digital hybrid masterslice IC includes an analog circuit section formed by a CMOS analog section and an analog master section in which a plurality of basic blocks are arranged in array form, and a digital circuit section formed by a gate array section. The digital circuit section operates under a power source voltage lower than that supplied to the analog circuit section. The IC further includes a selector circuit disposed between the digital circuit section and the analog circuit section, for testing the analog circuit section and the digital circuit section independently from each other, and a level shift circuit disposed between the selector circuit and the analog master section, for amplifying an output level from the gate array section. The level shift circuit is fixedly built-in in a masterwafer substrate as a hard-macro. The arrangement ensures that there is no possibility of any digital noise entering the analog circuit.

Abstract: The sharp convex corners of a resistor region in a semiconductor body are typically "weak points" at which avalanche breakdowns are prone to occur due to the small space charge regions at such corners and the correspondingly concentrated electric fields. To avoid this an additional region of the same conductivity type is formed in the semiconductor body opposite each convex corner and spaced therefrom a distance such that the space charge region expanding outwardly from a corner zone as the reverse-bias voltage is increased reaches the associated additional region before any breakdown occurs. When the additional region is so reached it also becomes reverse-biased, and the resulting additional space charge region merges with that from the corner zone to provide an additive effect. The shape of the additional region may be complementary to that of the corner zone, or it may be circularly shaped and disposed radially outwardly from the corner zone.

Abstract: A vertical PNP transistor having a large withstand voltage is disclosed. On a P-type substrate, a N-type epitaxial layer is provided. A P-type isolation region is formed in the epitaxial layer as a closed-loop to isolate a portion of the epitaxial layer from the other portions thereof. A first N-type buried layer is formed in the isolated epitaxial layer at the interface of the epitaxial layer and the semiconductor layer so as to separate the two. A second P-type buried layer is provided on top of the first buried layer. A P-type collector region is formed as a second closed-loop in the epitaxial layer enclosed within the first closed-loop. A high N-type concentration region that permits great withstand voltage is formed as a closed-loop separating the first closed-loop and the second closed-loop regions. A P-type emitter region is formed in the epitaxial layer region enclosed within the second closed-loop. Without the emitter region, the device can be used as a diode.