Patents by Inventor Mamoru Kudo
Mamoru Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7730366Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.Type: GrantFiled: June 30, 2004Date of Patent: June 1, 2010Assignee: Sony CorporationInventors: Shinobu Nakamura, Mamoru Kudo, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu
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Patent number: 7578676Abstract: A semiconductor device includes a first plate member having a circuit surface on which a circuit is provided, a second plate member having a circuit surface on which a circuit is provided, a plurality of first flat plates disposed on the circuit surface of the first plate member, a first communicating section disposed on the circuit surface of the first plate member, a plurality of second flat plates disposed on the circuit surface of the second plate member, and a second communicating section disposed on the circuit surface of the second plate member. The first plate member and the second plate member are arranged so that a surface of the first plate member opposite to the circuit surface faces a surface of the second plate member opposite to the circuit surface.Type: GrantFiled: April 1, 2008Date of Patent: August 25, 2009Assignee: Sony CorporationInventors: Shunichi Sukegawa, Kenichi Shigenami, Mamoru Kudo
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Patent number: 7554186Abstract: A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet disposed on the first semiconductor package base. The second semiconductor package includes a second semiconductor package base having a second cavity formed therein, a second mount component mounted in the second cavity, and a second magnet disposed on the second semiconductor package base so as to adsorb the first magnet. The first semiconductor package and the second semiconductor package are stacked by an adsorption of magnetic force between the first magnet and the second magnet.Type: GrantFiled: April 28, 2008Date of Patent: June 30, 2009Assignee: Sony CorporationInventors: Mamoru Kudo, Kenichi Shigenami, Shunichi Sukegawa
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Publication number: 20080315386Abstract: A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet disposed on the first semiconductor package base. The second semiconductor package includes a second semiconductor package base having a second cavity formed therein, a second mount component mounted in the second cavity, and a second magnet disposed on the second semiconductor package base so as to adsorb the first magnet. The first semiconductor package and the second semiconductor package are stacked by an adsorption of magnetic force between the first magnet and the second magnet.Type: ApplicationFiled: April 28, 2008Publication date: December 25, 2008Applicant: Sony CorporationInventors: Mamoru KUDO, Kenichi Shigenami, Shunichi Sukegawa
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Patent number: 7469367Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then run-length counted with a virtual channel clock so as to extract data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.Type: GrantFiled: December 4, 2006Date of Patent: December 23, 2008Assignee: Sony CorporationInventors: Shinobu Nakamura, Mamoru Kudo, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu
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Publication number: 20080188096Abstract: A semiconductor device includes a first plate member having a circuit surface on which a circuit is provided, a second plate member having a circuit surface on which a circuit is provided, a plurality of first flat plates disposed on the circuit surface of the first plate member, a first communicating section disposed on the circuit surface of the first plate member, a plurality of second flat plates disposed on the circuit surface of the second plate member, and a second communicating section disposed on the circuit surface of the second plate member. The first plate member and the second plate member are arranged so that a surface of the first plate member opposite to the circuit surface faces a surface of the second plate member opposite to the circuit surface.Type: ApplicationFiled: April 1, 2008Publication date: August 7, 2008Applicant: SONY CORPORATIONInventors: Shunichi SUKEGAWA, Kenichi SHIGENAMI, Mamoru KUDO
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Patent number: 7351068Abstract: A semiconductor device includes a first plate member having a circuit surface on which a circuit is provided, a second plate member having a circuit surface on which a circuit is provided, a plurality of first flat plates disposed on the circuit surface of the first plate member, a first communicating section disposed on the circuit surface of the first plate member, a plurality of second flat plates disposed on the circuit surface of the second plate member, and a second communicating section disposed on the circuit surface of the second plate member. The first plate member and the second plate member are arranged so that a surface of the first plate member opposite to the circuit surface faces a surface of the second plate member opposite to the circuit surface.Type: GrantFiled: January 26, 2007Date of Patent: April 1, 2008Assignee: Sony CorporationInventors: Shunichi Sukegawa, Kenichi Shigenami, Mamoru Kudo
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Patent number: 7342986Abstract: A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.Type: GrantFiled: June 17, 2004Date of Patent: March 11, 2008Assignee: Sony CorporationInventors: Shinobu Nakamura, Mamoru Kudo, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu
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Patent number: 7315968Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.Type: GrantFiled: December 4, 2006Date of Patent: January 1, 2008Assignee: Sony CorporationInventors: Shinobu Nakamura, Mamoru Kudo, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu
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Publication number: 20070184677Abstract: A semiconductor device includes a first plate member having a circuit surface on which a circuit is provided, a second plate member having a circuit surface on which a circuit is provided, a plurality of first flat plates disposed on the circuit surface of the first plate member, a first communicating section disposed on the circuit surface of the first plate member, a plurality of second flat plates disposed on the circuit surface of the second plate member, and a second communicating section disposed on the circuit surface of the second plate member. The first plate member and the second plate member are arranged so that a surface of the first plate member opposite to the circuit surface faces a surface of the second plate member opposite to the circuit surface.Type: ApplicationFiled: January 26, 2007Publication date: August 9, 2007Applicant: SONY CORPORATIONInventors: Shunichi SUKEGAWA, Kenichi Shigenami, Mamoru Kudo
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Publication number: 20070094549Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.Type: ApplicationFiled: December 4, 2006Publication date: April 26, 2007Inventors: Shinobu Nakamura, Mamoru Kudo, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu
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Publication number: 20070088992Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.Type: ApplicationFiled: December 4, 2006Publication date: April 19, 2007Inventors: Shinobu Nakamura, Mamoru Kudo, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu
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Publication number: 20060098541Abstract: Redundancy of data recorded on a CD is lowered. For example, a bit pattern of coupling bits to be recorded on CD is determined in accordance with sub data. The coupling bits whose bit pattern is determined in this manner are inserted in recorded/encoded audio data (and subcodes) at predetermined positions. A code string obtained in this manner is recorded on a recording medium. The sub data can therefore be recorded by embedding it in the coupling bits which are essentially not related to data.Type: ApplicationFiled: July 4, 2003Publication date: May 11, 2006Applicant: Sony CorporationInventor: Mamoru Kudo
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Patent number: 6992958Abstract: In PLL circuits for reproducing a channel clock in synchronism with data read from a disk-shaped recording medium driven for rotation, the frequency dividing ratio of frequency dividers provided in desired signal paths is made changeable according to the reproduced signal format of a CD reproduced signal or a DVD reproduced signal, for example. Although the frequency of the channel clock in synchronism with the reproduced signal differs in different signal formats, the above configuration makes it possible to reproduce the channel clock properly in accordance with a plurality of signal formats only by the operation of changing the frequency dividing ratio in a PLL circuit.Type: GrantFiled: December 4, 2001Date of Patent: January 31, 2006Assignee: Sony CorporationInventors: Mamoru Kudo, Shinobu Nakamura
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Publication number: 20050022076Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.Type: ApplicationFiled: June 30, 2004Publication date: January 27, 2005Inventors: Shinobu Nakamura, Mamoru Kudo, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu
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Publication number: 20040264623Abstract: A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.Type: ApplicationFiled: June 17, 2004Publication date: December 30, 2004Inventors: Shinobu Nakamura, Mamoru Kudo, Satoru Ooshima, Jun Yamane, Hirofumi Shimizu
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Publication number: 20020105365Abstract: In PLL circuits for reproducing a channel clock in synchronism with data read from a disk-shaped recording medium driven for rotation, the frequency dividing ratio of frequency dividers provided in desired signal paths is made changeable according to the reproduced signal format of a CD reproduced signal or a DVD reproduced signal, for example. Although the frequency of the channel clock in synchronism with the reproduced signal differs in different signal formats, the above configuration makes it possible to reproduce the channel clock properly in accordance with a plurality of signal formats only by the operation of changing the frequency dividing ratio in a PLL circuit.Type: ApplicationFiled: December 4, 2001Publication date: August 8, 2002Inventors: Mamoru Kudo, Shinobu Nakamura