Abstract: Disclosed is a selective cell discard system in an ATM switch to transfer exchanging a cell input from a plurality of input ports to a plurality of output ports, for controlling the selective cell discard to guarantee QOS (quality of service) by controlling the order of cell discard or the read-out order of cells accumulated in cell buffer when a plenty of cells exceeding the exchange capability of the switch is input, the system having: a selective cell discard controller connected to each of the plurality of input ports; a first-stage switch unit comprising all of cell buffers for output port group provided corresponding to output port groups into which the plurality of output ports are divided, and a cell multiplexer which inputs exchanging all of cells to be input from the plurality of input ports through the selective cell discard controller according to routing information of concerned cells; a groups of second-stage switch units which are provided corresponding to each of the cell buffers for output po

Abstract: In a main signal memory supervisory control system which comprises a parity generator, a parity detector, a write address counter and a read address counter, a state management section, a down counter, and a change point detector are arranged as memory supervising means. In this memory supervisory, a state management section receives address generation notifications from the write address counter and the read address counter to calculate and outputs the data accumulation amount of the main signal memory, a down counter subtracts a counter by the read address, sets a predetermined value of a data amount in advance, outputs a change notification when a counter value changes from numerical value "1" to numerical value "0", and loads the predetermined value on the counter, and a change point detector sends an odd-even switching signal of a parity when the change point detector receives the change notification.

Abstract: In a switching system of multiple time slot interchangers associated with outlet ports, each interchanger includes multiple data memories respectively connected to inlet ports and connected to the outlet port with which the interchanger is associated. A set of commands is established for each incoming data signal. The command set includes an inlet port number (IPN), an incoming slot number (ISN), an outlet port number (OPN), and an outgoing slot number (OSN). During a write cycle, one of the inlet ports is selected in accordance with the IPN command and one of the data memories which are associated with the selected inlet port is selected in accordance with the OPN command. The selected data memory is caused to store the data signal of an incoming time slot identified by the stored ISN command into one of its storage locations identified by the stored ISN command.