Abstract: Disclosed herein is an apparatus that includes a first wiring layer including a first bit line extending in a first direction, a first sense amplifier configured to amplify a potential of the first bit line, and a first transistor configured to supply an operation voltage to the first sense amplifier when a first control signal supplied to a gate electrode of the first transistor is activated. The first wiring layer further includes a first pattern coupled to the gate electrode of the first transistor and a second pattern having a first section arranged between the first bit line and the first pattern in a second direction perpendicular to the first direction.

Abstract: An apparatus that includes: a plurality of first data amplifiers arranged in line in a first direction; a plurality of first read data buses each coupled to a corresponding one of the plurality of first data amplifiers, the plurality of first read data buses having different lengths one another; and a plurality of first write data buses each coupled to the corresponding one of the plurality of first data amplifiers, the plurality of first write data buses having different lengths one another. The plurality of first read data buses and the plurality of first write data buses are alternately arranged in parallel in a second direction vertical to the first direction. The plurality of first read data buses are arranged in longest order and the plurality of first write data buses are arranged in shortest order.

Abstract: Drivers for sense amplifiers are disclosed. A driver may include two or more drain areas extending in a first direction and two or more source areas extending in the first direction. The driver may also include a drain interconnection including two or more first drain-interconnection portions which extend in the first direction above the two of more drain areas and one or more second drain-interconnection portions extending in a second direction between the two or more first drain-interconnection portions. The driver may also include a source interconnection including two or more first source-interconnection portions extending in the first direction above the two or more source areas and one or more second source-interconnection portions extending in the second direction between the two or more first source-interconnection portions. Associated systems are also disclosed.

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including a first bit line extending in a first direction, a first sense amplifier configured to amplify a potential of the first bit line, and a first transistor configured to supply an operation voltage to the first sense amplifier when a first control signal supplied to a gate electrode of the first transistor is activated. The first wiring layer further includes a first pattern coupled to the gate electrode of the first transistor and a second pattern having a first section arranged between the first bit line and the first pattern in a second direction perpendicular to the first direction.

Abstract: Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.

Abstract: Drivers for sense amplifiers are disclosed. A driver may include two or more drain areas extending in a first direction and two or more source areas extending in the first direction. The driver may also include a drain interconnection including two or more first drain-interconnection portions which extend in the first direction above the two of more drain areas and one or more second drain-interconnection portions extending in a second direction between the two or more first drain-interconnection portions. The driver may also include a source interconnection including two or more first source-interconnection portions extending in the first direction above the two or more source areas and one or more second source-interconnection portions extending in the second direction between the two or more first source-interconnection portions. Associated systems are also disclosed.

Abstract: Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.

Abstract: Drivers for sense amplifiers are disclosed. A driver may include two or more drain areas extending in a first direction and two or more source areas extending in the first direction. The driver may also include a drain interconnection including two or more first drain-interconnection portions which extend in the first direction above the two of more drain areas and one or more second drain-interconnection portions extending in a second direction between the two or more first drain-interconnection portions. The driver may also include a source interconnection including two or more first source-interconnection portions extending in the first direction above the two or more source areas and one or more second source-interconnection portions extending in the second direction between the two or more first source-interconnection portions. Associated systems are also disclosed.

Abstract: Drivers for sense amplifiers are disclosed. A driver may include two or more drain areas extending in a first direction and two or more source areas extending in the first direction. The driver may also include a drain interconnection including two or more first drain-interconnection portions which extend in the first direction above the two of more drain areas and one or more second drain-interconnection portions extending in a second direction between the two or more first drain-interconnection portions. The driver may also include a source interconnection including two or more first source-interconnection portions extending in the first direction above the two or more source areas and one or more second source-interconnection portions extending in the second direction between the two or more first source-interconnection portions. Associated systems are also disclosed.

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including a first power line extending in a first direction, a second wiring layer including second and third power lines extending in a second direction, a third wiring layer including power electrode patterns arranged in the second direction, and a fourth wiring layer including a fourth power line extending in the second direction. The first and second power lines are connected by a first via electrode. The first and third power lines are connected by a second via electrode. The second power line and each of the power electrode patterns are connected by a third via electrode. The third power line and each of the power electrode patterns are connected by a fourth via electrode. The fourth power line and each of the power electrode patterns are connected by a fifth via electrode.

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including a first power line extending in a first direction, a second wiring layer including second and third power lines extending in a second direction, a third wiring layer including power electrode patterns arranged in the second direction, and a fourth wiring layer including a fourth power line extending in the second direction. The first and second power lines are connected by a first via electrode. The first and third power lines are connected by a second via electrode. The second power line and each of the power electrode patterns are connected by a third via electrode. The third power line and each of the power electrode patterns are connected by a fourth via electrode. The fourth power line and each of the power electrode patterns are connected by a fifth via electrode.

Abstract: The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.

Abstract: Disclosed herein is an apparatus that includes a first wiring layer including a first power line extending in a first direction, a second wiring layer including second and third power lines extending in a second direction, a third wiring layer including power electrode patterns arranged in the second direction, and a fourth wiring layer including a fourth power line extending in the second direction. The first and second power lines are connected by a first via electrode. The first and third power lines are connected by a second via electrode. The second power line and each of the power electrode patterns are connected by a third via electrode. The third power line and each of the power electrode patterns are connected by a fourth via electrode. The fourth power line and each of the power electrode patterns are connected by a fifth via electrode.

Abstract: The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.

Abstract: Apparatuses for controlling defective bit lines in a semiconductor device are described. An example apparatus includes: a first region including a plurality of bit lines, a plurality of word lines and a plurality of memory cells, each memory cell is coupled to an associated bit line and an associated word line; a second region including a plurality of sense amplifiers, each sense amplifier includes a sense node and a column selection switch coupled to the sense node; a third region including a plurality of bleeder circuits, and disposed between the first and second regions; and a plurality of column selection lines. Each bit line from the first region to the second region is coupled to the sense node of an associated one of the plurality of sense amplifiers, and each column selection line from the column selection switch is coupled to an associated bleeder circuit.

Abstract: The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.

Abstract: The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.

Abstract: Apparatuses for controlling defective bit lines in a semiconductor device are described. An example apparatus includes: a first region including a plurality of bit lines, a plurality of word lines and a plurality of memory cells, each memory cell is coupled to an associated bit line and an associated word line; a second region including a plurality of sense amplifiers, each sense amplifier includes a sense node and a column selection switch coupled to the sense node; a third region including a plurality of bleeder circuits, and disposed between the first and second regions; and a plurality of column selection lines. Each bit line from the first region to the second region is coupled to the sense node of an associated one of the plurality of sense amplifiers, and each column selection line from the column selection switch is coupled to an associated bleeder circuit.

Abstract: Apparatuses for controlling defective bit lines in a semiconductor device are described. An example apparatus includes: a first region including a plurality of bit lines, a plurality of word lines and a plurality of memory cells, each memory cell is coupled to an associated bit line and an associated word line; a second region including a plurality of sense amplifiers, each sense amplifier includes a sense node and a column selection switch coupled to the sense node; a third region including a plurality of bleeder circuits, and disposed between the first and second regions; and a plurality of column selection lines. Each bit line from the first region to the second region is coupled to the sense node of an associated one of the plurality of sense amplifiers, and each column selection line from the column selection switch is coupled to an associated bleeder circuit.

Abstract: A semiconductor device has a first and second transistors formed on an active region defined by an insulating region. The active region is divided into a first and second portions arranged in a first direction, and into a third and fourth portions interposed between the first portion and the second portion, and provided adjacent to each other in a second direction orthogonal to the first direction. The first transistor is provided in the first and third portions, and the second transistor is provided in the second and fourth portions.