Patents by Inventor Mamoru Sobue

Mamoru Sobue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for inspecting element layout in semiconductor device
    Publication number: 20070234262
    Abstract: A method for inspecting the layout of elements included in a semiconductor device. The method includes setting paired layout inspection requirements including at least an element interval at which a paired layout is enabled, inspecting whether or not the elements that are to be inspected for paired layout satisfy the paired layout inspection requirements, setting a search area for each of the elements that are to be inspected for paired layout, and extracting figures included in the search areas of the elements that are to be inspected for paired layout and inspecting whether or not the extracted figures of the elements that are to be inspected for paired layout are congruent to each other.
    Type: Application
    Filed: September 19, 2006
    Publication date: October 4, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Masato Uedi, Mamoru Sobue, Kouhei Nagaya, Takeshi Inoue, Yoshinori Gotou
  • Output circuit comprising bipolar transistors for driving CMOS circuit to reduce power consumption of the output circuit and avoid erroneous operation of the CMOS circuit
    Patent number: 5394038
    Abstract: An output circuit, having a plurality of bipolar transistors for driving a CMOS circuit, comprises an output level maintaining transistor connected between an output terminal of the output circuit and ground. The output level maintaining transistor maintains a level of the output terminal at a specific high potential by transmitting a current from the output terminal to the ground when the output circuit is outputting a high level signal to the output terminal, and the output level maintaining transistor is cut OFF when the output circuit is outputting a low level signal to the output terminal. Consequently, the output circuit according to the present invention reduces power consumption of the output circuit and avoids erroneous operation of the CMOS circuit.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: February 28, 1995
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Mamoru Sobue, Katsuya Shimizu