Abstract: Disclosed herein is an information processing apparatus including: a computation block configured, so as to make an error of a VBV occupation amount of a VBV occupation amount target picture next to base data that is variable-length encoded data to be replaced by replacing data greater than an actual value, to compute the VBV occupation amount of the VBV occupation amount target picture from a VBV delay of the VBV occupation amount target picture; and an encoding block configured to variable-length encode the replacing data on the basis of the VBV occupation amount of the VBV occupation amount target picture computed by the computation block.

Abstract: Encoding parameters of picture and higher layers of importance to a number of applications, and encoding parameters of slice and lower layers of no importance to all applications are converted into auxiliary packets inserted respectively into a V-blanking area and an H-blanking area of a video-data signal output by a history-information-multiplexing apparatus employed in a video-decoding system. On the other hand, a video-encoding system extracts back the auxiliary packets superposed on the V-blanking area and the H-blanking area from an input base-band video signal. As a result, a technique of superposing information on data can be changed in accordance with the importance of the information and required information can be fetched with ease.

Abstract: Disclosed herein is an information processing apparatus including: a computation block configured, so as to make an error of a VBV occupation amount of a VBV occupation amount target picture next to base data that is variable-length encoded data to be replaced by replacing data greater than an actual value, to compute the VBV occupation amount of the VBV occupation amount target picture from a VBV delay of the VBV occupation amount target picture; and an encoding block configured to variable-length encode the replacing data on the basis of the VBV occupation amount of the VBV occupation amount target picture computed by the computation block.

Abstract: A slice decoder control circuit sequentially supplies the parameter of the picture layer and the write pointer of a first slice to a first slice decoder, the parameter of the picture layer and the write pointer of a second slice to a second slice decoder, and the parameter of the picture layer and the write pointer of a third slice to a third slice decoder, and causes the slice decoders to decode the respective parameters and write pointers. On the basis of the input of signals indicating the completion of decoding processing inputted from the slice decoders, the slice decoder control circuit supplies the write pointer of a fourth slice to the second decoder and causes the second slice decoder to decode the write pointer at timing A, and supplies the write pointer of a fifth slice to the third decoder and causes the third slice decoder to decode the write pointer at timing B. Subsequently, the similar processing is repeated until the last slice is decoded.

Abstract: A ferroelectric memory includes a base member, a first dielectric layer formed above the base member, a second dielectric layer formed above the first dielectric layer, a contact hole that penetrates the first and second dielectric layers, a plug formed in the contact hole, and a barrier layer formed above the plug, and a ferroelectric capacitor formed from a lower electrode, a ferroelectric layer and an upper electrode successively laminated in a region including above the plug. The second dielectric layer has a property that is more difficult to be polished than the plug and the first dielectric layer.

Abstract: A video decoder reproduces an MP@ML/MPEG-2 video bit stream at an arbitrary speed. When a slice decoder control circuit receives parameters, the slice decoder control circuit sequentially supplies parameters of a picture layer and a write pointer associated with a first slice to a first slice decoder, the parameters of the picture layer and a write pointer associated with a second slice to a second slice decoder, the parameters of the picture layer and a write pointer associated with a third slice to a third slice decoder, so that the slices are decoded by the respective slice decoders. On the basis of signals indicating completion of decoding, received from the first to third slice decoders, the slice decoder control circuit gives commands the first to third slice decoders to decode particular slices.

Abstract: A ferroelectric memory includes a base member, a first dielectric layer formed above the base member, a second dielectric layer formed above the first dielectric layer, a contact hole that penetrates the first and second dielectric layers, a plug formed in the contact hole, and a barrier layer formed above the plug, and a ferroelectric capacitor formed from a lower electrode, a ferroelectric layer and an upper electrode successively laminated in a region including above the plug. The second dielectric layer has a property that is more difficult to be polished than the plug and the first dielectric layer.

Abstract: Encoding parameters of picture and higher layers of importance to a number of applications, and encoding parameters of slice and lower layers of no importance to all applications are converted into auxiliary packets inserted respectively into a V-blanking area and an H-blanking area of a video-data signal output by a history-information-multiplexing apparatus employed in a video-decoding system. On the other hand, a video-encoding system extracts back the auxiliary packets superposed on the V-blanking area and the H-blanking area from an input base-band video signal. As a result, a technique of superposing information on data can be changed in accordance with the importance of the information and required information can be fetched with ease.

Abstract: Encoding parameters of picture and higher layers of importance to a number of applications, and encoding parameters of slice and lower layers of no importance to all applications are converted into auxiliary packets inserted respectively into a V-blanking area and an H-blanking area of a video-data signal output by a history-information-multiplexing apparatus employed in a video-decoding system. On the other hand, a video-encoding system extracts back the auxiliary packets superposed on the V-blanking area and the H-blanking area from an input base-band video signal. As a result, a technique of superposing information on data can be changed in accordance with the importance of the information and required information can be fetched with ease.

Abstract: A ferroelectric memory includes a base member, a first dielectric layer formed above the base member, a second dielectric layer formed above the first dielectric layer, a contact hole that penetrates the first and second dielectric layers, a plug formed in the contact hole, and a barrier layer formed above the plug, and a ferroelectric capacitor formed from a lower electrode, a ferroelectric layer and an upper electrode successively laminated in a region including above the plug. The second dielectric layer has a property that is more difficult to be polished than the plug and the first dielectric layer.

Abstract: A ferroelectric memory includes a base member, a dielectric layer formed above the base member, a contact hole that penetrates the dielectric layer, a plug formed inside the contact hole, a barrier layer formed above the plug, and including a first portion with a portion formed in the contact hole and a second portion formed integrally with the first portion and above the dielectric layer, and a ferroelectric capacitor formed from a lower electrode, a ferroelectric layer and an upper electrode successively laminated in a region including above the plug.

Abstract: In a signal processing apparatus having a plurality of signal processing circuits where predetermined data is to be output sequentially through the plurality of signal processing circuits, when signal processing is performed at each signal processing circuit, timing necessary for respective signal processing is added to the data to be transmitted, as a header information, so that a complicated construction, such that a circuit for obtaining timing necessary for signal processing is added at each signal processing circuit, can be avoided, and the data can be securely processed and delivered at each signal processing circuit.

Abstract: A method of and apparatus for identifying a signal transmitting source detects a switching of a signal on the reception side thereby to prevent a transmission error from occurring when a signal is switched. The apparatus for identifying a signal transmitting source comprises a transmitting source identifying code extracting circuit for extracting a transmitting source identifying code provided in a SDDI format header of a received signal, a preceding transmitting source identifying code holding circuit for detecting a change of the transmitting source identifying code, and a transmitting source identifying code comparing circuit for detecting a switching of a transmitted signal based on the transmitting source identifying code thus changed, thereby detecting a switching of the transmitting source.

Abstract: In a method for manufacturing a semiconductor device that includes a memory region and a logic circuit region, the invention provides a dielectric layer that is better planarized upon polishing. The invention provides a semiconductor substrate having a conductive layer that is to become a word gate of the non-volatile semiconductor device, a stopper layer formed above the conductive layer, and sidewall-like control gates formed on both side surfaces of the conductive layer through ONO films above a semiconductor layer in a memory region, and a gate electrode of a dielectric gate field effect transistor formed above the semiconductor layer in a logic circuit region. A dielectric layer is formed over an entire surface of the memory region and the logic circuit region of the semiconductor substrate. A polishing restricting layer is formed above a part of the dielectric layer.

Abstract: In a signal processing apparatus having a plurality of signal processing circuits where predetermined data is to be output sequentially through the plurality of signal processing circuits, when signal processing is performed at each signal processing circuit, timing necessary for respective signal processing is added to the data to be transmitted, as a header information, so that a complicated construction, such that a circuit for obtaining timing necessary for signal processing is added at each signal processing circuit, can be avoided, and the data can be securely processed and delivered at each signal processing circuit.

Abstract: A method of and apparatus for identifying a signal transmitting source detects a switching of a signal on the reception side thereby to prevent a transmission error from occurring when a signal is switched. The apparatus for identifying a signal transmitting source comprises a transmitting source identifying code extracting circuit for extracting a transmitting source identifying code provided in a SDDI format header of a received signal, a preceding transmitting source identifying code holding circuit for detecting a change of the transmitting source identifying code, and a transmitting source identifying code comparing circuit for detecting a switching of a transmitted signal based on the transmitting source identifying code thus changed, thereby detecting a switching of the transmitting source.

Abstract: In a method for manufacturing a semiconductor device that includes a memory region and a logic circuit region, the invention provides a dielectric layer that is better planarized upon polishing. The invention provides a semiconductor substrate having a conductive layer that is to become a word gate of the non-volatile semiconductor device, a stopper layer formed above the conductive layer, and sidewall-like control gates formed on both side surfaces of the conductive layer through ONO films above a semiconductor layer in a memory region, and a gate electrode of a dielectric gate field effect transistor formed above the semiconductor layer in a logic circuit region. A dielectric layer is formed over an entire surface of the memory region and the logic circuit region of the semiconductor substrate. A polishing restricting layer is formed above a part of the dielectric layer.

Abstract: Encoding parameters of picture and higher layers of importance to a number of applications, and encoding parameters of slice and lower layers of no importance to all applications are converted into auxiliary packets inserted respectively into a V-blanking area and an H-blanking area of a video-data signal output by a history-information-multiplexing apparatus employed in a video-decoding system. On the other hand, a video-encoding system extracts back the auxiliary packets superposed on the V-blanking area and the H-blanking area from an input base-band video signal. As a result, a technique of superposing information on data can be changed in accordance with the importance of the information and required information can be fetched with ease.

Abstract: Encoding parameters of picture and higher layers of importance to a number of applications, and encoding parameters of slice and lower layers of no importance to all applications are converted into auxiliary packets inserted respectively into a V-blanking area and an H-blanking area of a video-data signal output by a history-information-multiplexing apparatus employed in a video-decoding system. On the other hand, a video-encoding system extracts back the auxiliary packets superposed on the V-blanking area and the H-blanking area from an input base-band video signal. As a result, a technique of superposing information on data can be changed in accordance with the importance of the information and required information can be fetched with ease.