Patents by Inventor Man Fai Ng
Man Fai Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160260841Abstract: A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.Type: ApplicationFiled: March 6, 2015Publication date: September 8, 2016Inventors: Bin YANG, Man Fai NG
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Patent number: 8987110Abstract: A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.Type: GrantFiled: May 9, 2012Date of Patent: March 24, 2015Assignee: Globalfoundries, Inc.Inventors: Man Fai Ng, Bin Yang
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Publication number: 20140183720Abstract: Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Scott Beasor, Jay Strane, Man Fai Ng, Brett H. Engel, Chang Yong Xiao, Michael P. Belyansky, Tsung-Liang Chen, Kyung Bum Koo
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Patent number: 8765537Abstract: A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top.Type: GrantFiled: September 7, 2012Date of Patent: July 1, 2014Assignee: Globalfoundries Inc.Inventors: Man Fai Ng, Bin Yang
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Patent number: 8680624Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.Type: GrantFiled: June 4, 2012Date of Patent: March 25, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Man Fai Ng, Bin Yang
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Patent number: 8674438Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a <100> crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.Type: GrantFiled: February 12, 2013Date of Patent: March 18, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Bin Yang, Man Fai Ng
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Publication number: 20130320447Abstract: A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.Type: ApplicationFiled: August 9, 2013Publication date: December 5, 2013Applicant: GLOBALFOUNDERIES Inc.Inventors: Bin YANG, Man Fai NG
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Publication number: 20130249000Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.Type: ApplicationFiled: May 20, 2013Publication date: September 26, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Bin Yang, Man Fai Ng
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Patent number: 8518758Abstract: A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.Type: GrantFiled: March 18, 2010Date of Patent: August 27, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Bin Yang, Man Fai Ng
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Patent number: 8445342Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.Type: GrantFiled: June 23, 2010Date of Patent: May 21, 2013Assignee: Globalfoundries Inc.Inventors: Bin Yang, Man Fai Ng
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Patent number: 8394691Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a <100> crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.Type: GrantFiled: June 11, 2010Date of Patent: March 12, 2013Assignee: Globalfoundries, Inc.Inventors: Bin Yang, Man Fai Ng
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Patent number: 8390042Abstract: Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.Type: GrantFiled: January 18, 2012Date of Patent: March 5, 2013Assignee: Globalfoundries Inc.Inventors: Man Fai Ng, Rohit Pal
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Publication number: 20130005128Abstract: A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top.Type: ApplicationFiled: September 7, 2012Publication date: January 3, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Man Fai NG, Bin Yang
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Patent number: 8329515Abstract: An eFUSE is formed with a gate stack including a layer of embedded silicon germanium (eSiGe) on the polysilicon. An embodiment includes forming a shallow trench isolation (STI) region in a substrate, forming a first gate stack on the substrate for a PMOS device, forming a second gate stack on an STI region for an eFUSE, forming first embedded silicon germanium (eSiGe) on the substrate on first and second sides of the first gate stack, and forming second eSiGe on the second gate stack. The addition of eSiGe to the eFUSE gate stack increases the distance between the eFUSE debris zone and an underlying metal gate, thereby preventing potential shorting.Type: GrantFiled: December 28, 2009Date of Patent: December 11, 2012Assignee: Globalfoundries Inc.Inventors: Bin Yang, Man Fai Ng
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Publication number: 20120235237Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.Type: ApplicationFiled: June 4, 2012Publication date: September 20, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Man Fai NG, Bin YANG
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Publication number: 20120220095Abstract: A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.Type: ApplicationFiled: May 9, 2012Publication date: August 30, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Man Fai NG, Bin YANG
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Patent number: 8222093Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.Type: GrantFiled: February 17, 2010Date of Patent: July 17, 2012Assignee: Globalfoundries, Inc.Inventors: Man Fai Ng, Bin Yang
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Patent number: 8198170Abstract: A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.Type: GrantFiled: October 15, 2010Date of Patent: June 12, 2012Assignee: GLOBALFOUNDRIES, Inc.Inventors: Man Fai Ng, Bin Yang
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Publication number: 20120119308Abstract: Improved semiconductor devices including metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.Type: ApplicationFiled: January 18, 2012Publication date: May 17, 2012Applicant: GLOBALFOUNDRIES Inc.Inventors: Man Fai NG, Rohit Pal
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Publication number: 20120094466Abstract: A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Inventors: Man Fai NG, Bin YANG