Abstract: A data storage system having a packet switching network, a cache memory, and a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors and cache memory are interconnected through the packet switching network. Each one of the directors is adapted to transmit different types of information packets to another one of the directors through the network. Each one of the directors is adapted to transmit and receive different types of information packets to another one of the directors or cache memories through the packet switching network. Each one of the cache memories is adapted to receive and transmit different types of information packets to one of the directors through the packet switching network. One type of information packet requires a different degree of latency than another type of information packet.

Abstract: A method is provided for performing arbitration in an information packet controller. The method includes transmitting different types of information packets from an initiator to a receiver. One type of information packet has a quality of service requiring a faster transmission time from the initiator to the receiver than another type of information packet having a quality of service having a slower transmission time from the initiator to the receiver. The transmitting of the information packets from the initiator to the receiver is in accordance with priority assigned to the information packet, the quality of service assigned to the information packet, and the age of such information packets having been stored in a queue of the initiator, such quality of service being a function of the speed at which the packets are required to pass from the initiator to a receiver.

Abstract: A plurality of state machines arranged into three functional units, an Upper Machine, Middle Machine and a Lower Machine facilitate movement of user data between a buffer memory and a Global Memory (GM) in a data transfer interface. The Middle Machine controls all data movement to and from the GM. Although not directly in the data path, it is responsible for coordinating control between elements that comprise data transfer channels. The Middle Machine is interconnected to and provides control and coordination between the Upper and Lower sides of the buffer memory. The Lower Machine connects to a data assembly mechanism of each pipe. The Upper Machine connects to the backplane, which in turn connects to Global Memory. The actual data transfers between the buffer memory and GM are controlled by the Upper Machine, and transfers between the buffer memory and the data assembly mechanism are controlled by the Lower Machine.