Patents by Inventor Man Mui
Man Mui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9959915Abstract: The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.Type: GrantFiled: May 11, 2016Date of Patent: May 1, 2018Assignee: SanDisk Technologies LLCInventors: Amul Desai, Hao Nguyen, Man Mui, Ohwon Kwon
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Patent number: 9947395Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.Type: GrantFiled: April 13, 2017Date of Patent: April 17, 2018Assignee: SanDisk Technologies LLCInventors: Kenneth Louie, Man Mui
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Patent number: 9947407Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.Type: GrantFiled: May 19, 2017Date of Patent: April 17, 2018Assignee: SanDisk Technologies LLCInventors: Hao Nguyen, Man Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong
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Publication number: 20170256317Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.Type: ApplicationFiled: May 19, 2017Publication date: September 7, 2017Applicant: SanDisk Technologies LLCInventors: Hao Nguyen, Man Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong
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Publication number: 20170221556Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.Type: ApplicationFiled: April 13, 2017Publication date: August 3, 2017Inventors: Kenneth Louie, Man Mui
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Publication number: 20170169867Abstract: The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.Type: ApplicationFiled: May 11, 2016Publication date: June 15, 2017Applicant: SanDisk Technologies, LLCInventors: Amul DESAI, Hao Nguyen, Man Mui, Ohwon Kwon
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Patent number: 9659656Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.Type: GrantFiled: March 7, 2016Date of Patent: May 23, 2017Assignee: SanDisk Technologies LLCInventors: Hao Nguyen, Man Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong
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Patent number: 9633742Abstract: In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.Type: GrantFiled: July 10, 2014Date of Patent: April 25, 2017Assignee: SanDisk Technologies LLCInventors: Amul Dhirajbhai Desai, Hao Nguyen, Seungpil Lee, Man Mui
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Patent number: 9627046Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.Type: GrantFiled: March 2, 2015Date of Patent: April 18, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Kenneth Louie, Man Mui
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Patent number: 9595338Abstract: In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.Type: GrantFiled: September 24, 2014Date of Patent: March 14, 2017Assignee: SanDisk Technologies LLCInventors: Juan Carlos Lee, Hao Nguyen, Man Mui, Tien-chien Kuo, Yuki Mizutani
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Patent number: 9502471Abstract: A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.Type: GrantFiled: August 25, 2015Date of Patent: November 22, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhenyu Lu, Henry Chien, Johann Alsmeier, Koji Miyata, Tong Zhang, Man Mui, James Kai, Wenguang Shi, Wei Zhao, Xiaolong Hu, Jiyin Xu, Gerrit Jan Hemink, Christopher Petti
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Publication number: 20160260476Abstract: Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.Type: ApplicationFiled: March 2, 2015Publication date: September 8, 2016Inventors: Kenneth Louie, Man Mui
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Publication number: 20160189778Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Applicant: SanDisk Technologies, Inc.Inventors: Hao NGUYEN, Man MUI, Khanh NGUYEN, Seungpil LEE, Toru ISHIGAKI, Yingda DONG
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Patent number: 9318210Abstract: When applying a sensing voltage at one end of a word line of a non-volatile memory circuit, an initial kick, where the voltage is initially raised somewhat above its final desired voltage, is used. Using on-chip circuitry for the determination of the RC time constant of the word lines allows for this kick to be trimmed to the specifics of the circuit. To further improve settling times for read operations is NAND type architectures, when raising the voltage to the desired read level on a selected word line, a reverse kick, where the non-selected word line's voltage is dropped briefly, can be applied to neighboring non-selected word lines.Type: GrantFiled: February 2, 2015Date of Patent: April 19, 2016Assignee: SanDisk Technologies Inc.Inventors: James V. Hart, Kenneth Louie, Khanh Nguyen, Man Mui
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Patent number: 9312026Abstract: In a three-dimensional nonvolatile memory, when a block erase failure occurs, zones within a block may be separately verified to see if some zones pass verification. Zones that pass may be designated as good zones and may subsequently be used to store user data while bad zones in the same block may be designated as bad and may not be used for subsequent storage of user data.Type: GrantFiled: August 22, 2014Date of Patent: April 12, 2016Assignee: SanDisk Technologies Inc.Inventors: Mrinal Kochar, Gautam Dusija, Chris Avila, Yingda Dong, Man Mui, Yichao Huang, Deepak Raghu
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Patent number: 9305648Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.Type: GrantFiled: August 20, 2014Date of Patent: April 5, 2016Assignee: SanDisk Technologies, Inc.Inventors: Hao Nguyen, Man Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong
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Publication number: 20160086671Abstract: In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.Type: ApplicationFiled: September 24, 2014Publication date: March 24, 2016Inventors: Juan Carlos Lee, Hao Nguyen, Man Mui, Tien-chien Kuo, Yuki Mizutani
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Publication number: 20160055911Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.Type: ApplicationFiled: August 20, 2014Publication date: February 25, 2016Inventors: Hao Nguyen, Man Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong
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Publication number: 20160055918Abstract: In a three-dimensional nonvolatile memory, when a block erase failure occurs, zones within a block may be separately verified to see if some zones pass verification. Zones that pass may be designated as good zones and may subsequently be used to store user data while bad zones in the same block may be designated as bad and may not be used for subsequent storage of user data.Type: ApplicationFiled: August 22, 2014Publication date: February 25, 2016Inventors: Mrinal Kochar, Gautam Dusija, Chris Avila, Yingda Dong, Man Mui, Yichao Huang, Deepak Raghu
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Patent number: 9240241Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.Type: GrantFiled: December 8, 2014Date of Patent: January 19, 2016Assignee: SanDisk Technologies Inc.Inventors: Xiying Costa, Alexander Kwok-Tung Mak, Chris Avila, Gautam Dusija, Man Mui