Patents by Inventor Manabu Ishida

Manabu Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230411984
    Abstract: A power supply system includes a regulator, outputting a system voltage; a load, receiving the system voltage to operate; a battery, charged by the system voltage; a charging transistor, receiving the system voltage and controlling a charging current to the battery; and a three-input amplifier, in which three factors including a charging current detection value, a reference charging current, and a reference limit current determined according to a difference between the system voltage and a minimum system voltage are input, and which obtains an output corresponding to a difference between the reference charging current and the charging current detection value when the reference charging current is equal to or less than the reference limit current, and obtains an output corresponding to a difference between the reference limit current and the charging current detection value when the reference charging current exceeds the reference limit current.
    Type: Application
    Filed: July 26, 2022
    Publication date: December 21, 2023
    Inventor: MANABU ISHIDA
  • Patent number: 11163148
    Abstract: A telescope system includes a telescope and a selective shielding unit including at least one member including a passage allowable region for an observation target electromagnetic wave and a passage blocking region for the observation target electromagnetic wave. The telescope includes a position detectable detector that detects the observation target electromagnetic wave on a surface different from a focal plane of the telescope. The selective shielding unit is disposed on a front side of the detector. Patterns of the passage allowable region and the passage blocking region of the at least one member and disposition of the at least one member are set to allow for reconstruction of an observation image based on an image detected in the detector.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 2, 2021
    Assignee: Japan Aerospace Exploration Agency
    Inventors: Yoshitomo Maeda, Manabu Ishida, Ryo Iizuka, Takayuki Hayashi
  • Publication number: 20210048457
    Abstract: Implementations of a comparator system may include a first transistor including a gate where the gate is configured to be coupled to a resistor-capacitor (RC) noise filter coupled to a resistor. The first transistor may be included in a PMOS differential pair. A first offset resistor may be coupled to the source of the first transistor and to a source of a second transistor included in the PMOS differential pair. A second offset resistor may be coupled between the first transistor and the second transistor. A voltage difference between a first back gate bias voltage of the first transistor and a second back gate bias voltage of the second transistor may indicate a current value through the resistor.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Manabu ISHIDA
  • Publication number: 20200371140
    Abstract: Implementations of a comparator system may include a first transistor including a gate where the gate is configured to be coupled to a resistor-capacitor (RC) noise filter coupled to a resistor. The first transistor may be included in a PMOS differential pair. A first offset resistor may be coupled to the source of the first transistor and to a source of a second transistor included in the PMOS differential pair. A second offset resistor may be coupled between the first transistor and the second transistor. A voltage difference between a first back gate bias voltage of the first transistor and a second back gate bias voltage of the second transistor may indicate a current value through the resistor.
    Type: Application
    Filed: July 3, 2019
    Publication date: November 26, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Manabu ISHIDA
  • Patent number: 10823767
    Abstract: Implementations of a comparator system may include a first transistor including a gate where the gate is configured to be coupled to a resistor-capacitor (RC) noise filter coupled to a resistor. The first transistor may be included in a PMOS differential pair. A first offset resistor may be coupled to the source of the first transistor and to a source of a second transistor included in the PMOS differential pair. A second offset resistor may be coupled between the first transistor and the second transistor. A voltage difference between a first back gate bias voltage of the first transistor and a second back gate bias voltage of the second transistor may indicate a current value through the resistor.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Manabu Ishida
  • Publication number: 20200107736
    Abstract: A pulse wave measurement apparatus includes a light transmitting plate, a green light which casts green light, an infrared light which casts infrared light, a memory, and a processor coupled to the memory. The processor is configured to cause the green light to cast green light on the finger through the light transmitting plate, the green light having a peak wavelength in a wavelength range of 490 nm or more and 570 nm or less, detect an intensity of reflection of the casted green light from the finger, measure a pulse wave in the finger by making the infrared light cast infrared light on the finger through the light transmitting plate when the intensity of the reflection indicates that force at which the finger is pressed against the light transmitting plate is within a predetermined range suitable for the measurement of the pulse wave.
    Type: Application
    Filed: April 25, 2019
    Publication date: April 9, 2020
    Applicant: FUJITSU CONNECTED TECHNOLOGIES LIMITED
    Inventor: Manabu Ishida
  • Publication number: 20190384052
    Abstract: A telescope system includes a telescope and a selective shielding unit including at least one member including a passage allowable region for an observation target electromagnetic wave and a passage blocking region for the observation target electromagnetic wave. The telescope includes a position detectable detector that detects the observation target electromagnetic wave on a surface different from a focal plane of the telescope. The selective shielding unit is disposed on a front side of the detector. Patterns of the passage allowable region and the passage blocking region of the at least one member and disposition of the at least one member are set to allow for reconstruction of an observation image based on an image detected in the detector.
    Type: Application
    Filed: January 23, 2018
    Publication date: December 19, 2019
    Inventors: Yoshitomo MAEDA, Manabu ISHIDA, Ryo IIZUKA, Takayuki HAYASHI
  • Patent number: 10263440
    Abstract: In an electronic device, a monitoring circuit monitors a voltage change with regard to each of an RX2+ terminal and an RX2? terminal in a state where a charging device is connected to a Type-C connector. A determining circuit determines whether a short-circuit between a VBUS terminal and the RX2+ and RX2? terminals has occurred using the voltage change at each of the RX2+ terminal and the RX2? terminal.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 16, 2019
    Assignee: FUJITSU CONNECTED TECHNOLOGIES LIMITED
    Inventor: Manabu Ishida
  • Publication number: 20180054072
    Abstract: In an electronic device, a monitoring circuit monitors a voltage change with regard to each of an RX2+ terminal and an RX2? terminal in a state where a charging device is connected to a Type-C connector. A determining circuit determines whether a short-circuit between a VBUS terminal and the RX2+ and RX2? terminals has occurred using the voltage change at each of the RX2+ terminal and the RX2? terminal.
    Type: Application
    Filed: June 28, 2017
    Publication date: February 22, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Manabu Ishida
  • Patent number: 9468259
    Abstract: A sock includes a knitted fabric covering at least from a toe portion to a heel portion of a wearer. The knitted fabric, which is arranged in a first region covering at least sections, in a sole, corresponding to phalanges and metatarsal heads of the wearer, is formed by stitches that are knitted only by means of a covering yarn, which is a winding yarn wrapped around a core yarn.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: October 18, 2016
    Assignee: OKAMOTO CORPORATION
    Inventors: Manabu Ishida, Takahiro Araki, Emi Fujita
  • Patent number: 8824631
    Abstract: Provided is a technique for X-ray reflection, such as an X-ray reflecting mirror, capable of achieving a high degree of smoothness of a reflecting surface, high focusing (reflecting) performance, stability in a curved surface shape, and a reduction in overall weight. A silicon plate (silicon wafer) is subjected to thermal plastic deformation to form an X-ray reflecting mirror having a reflecting surface with a stable curved surface shape. The silicon wafer can be deformed to any shape by applying a pressure thereto in a hydrogen atmosphere at a high temperature of about 1300° C. The silicon plate may be simultaneously subjected to hydrogen annealing to further reduce roughness of a silicon surface to thereby provide enhanced reflectance.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: September 2, 2014
    Assignees: Japan Aerospace Exploration Agency, Tokyo Manufacturing University
    Inventors: Kazuhisa Mitsuda, Manabu Ishida, Yuichiro Ezoe, Kazuo Nakajima
  • Publication number: 20130233025
    Abstract: A sock includes a knitted fabric covering at least from a toe portion to a heel portion of a wearer. The knitted fabric, which is arranged in a first region covering at least sections, in a sole, corresponding to phalanges and metatarsal heads of the wearer, is formed by stitches that are knitted only by means of a covering yarn, which is a winding yarn wrapped around a core yarn.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 12, 2013
    Applicant: OKAMOTO CORPORATION
    Inventors: Manabu ISHIDA, Takahiro Araki, Emi Fujita
  • Patent number: 7965125
    Abstract: A current drive circuit allows for a reduction in chip size and prevents an output current from decreasing. The current drive circuit has an output terminal connected to a first resistor. The first resistor is connected to a second resistor and the drain of a first transistor. The gate of the first transistor is connected to the gate of a second transistor, a grounded first current source, and the source of a third transistor. A second current source and the third transistor are connected to a power supply line. The second current source is connected to the gate of the third transistor, the drain of a fourth transistor, the drain of a fifth transistor, and a second resistor. When the voltage decreases, the on resistance of the fourth transistor increases, the fifth transistor is then connected in series to the second transistor, which increases the gate voltage of the first transistor.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 21, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Manabu Ishida
  • Publication number: 20110110499
    Abstract: Provided is a technique for X-ray reflection, such as an X-ray reflecting mirror, capable of achieving a high degree of smoothness of a reflecting surface, high focusing (reflecting) performance, stability in a curved surface shape, and a reduction in overall weight. A silicon plate (silicon wafer) is subjected to thermal plastic deformation to form an X-ray reflecting mirror having a reflecting surface with a stable curved surface shape. The silicon wafer can be deformed to any shape by applying a pressure thereto in a hydrogen atmosphere at a high temperature of about 1300° C. The silicon plate may be simultaneously subjected to hydrogen annealing to further reduce roughness of a silicon surface to thereby provide enhanced reflectance.
    Type: Application
    Filed: January 18, 2011
    Publication date: May 12, 2011
    Inventors: Kazuhisa MITSUDA, Manabu ISHIDA, Yuichiro EZOE, Kazuo NAKAJIMA
  • Publication number: 20100315037
    Abstract: A resistor testing circuit for a battery charger that tests divisional resistors used to estimate the resistance of a thermistor in a battery pack. The battery charger when activated conducts a self test. In the self test, switches are sequentially switched to form groups of resistors and test the connection state of the resistors groups. When a defect is detected by the self test, the battery charger stops performing charging. When no defects are detected by the self test, the thermistor of the battery pack is used to estimate temperature. The charging current is determined in correspondence with the temperature. Then, charging is started.
    Type: Application
    Filed: May 21, 2010
    Publication date: December 16, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Masami AIURA, Manabu Ishida, Noriaki Tanaka
  • Publication number: 20100244906
    Abstract: A current drive circuit allows for a reduction in chip size and prevents an output current from decreasing. The current drive circuit has an output terminal connected to a first resistor. The first resistor is connected to a second resistor and the drain of a first transistor. The gate of the first transistor is connected to the gate of a second transistor, a grounded first current source, and the source of a third transistor. A second current source and the third transistor are connected to a power supply line. The second current source is connected to the gate of the third transistor, the drain of a fourth transistor, the drain of a fifth transistor, and a second resistor. When the voltage decreases, the on resistance of the fourth transistor increases, the fifth transistor is then connected in series to the second transistor, which increases the gate voltage of the first transistor.
    Type: Application
    Filed: March 3, 2010
    Publication date: September 30, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventor: Manabu Ishida
  • Patent number: 7725673
    Abstract: When a file server is to create data that does not permit falsification in an external storage, it is not possible to guarantee that the rewriting of this data can be prevented from a computer connected to the external storage without going through a file server. Provided is a storage system configured from a first storage having a file I/O processing unit and a second storage connected to this first storage, wherein the first storage includes a unit for requesting a change of access authority to the storage area in the own storage and in the second storage provided to the own storage. An access request to a storage area in a second storage from a computer connected to a second storage without going through a file I/O processing unit is restricted based on the change of access authority executed by the second storage upon receiving the request from the first storage.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: May 25, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Manabu Ishida, Yohsuke Ishii
  • Patent number: 7613871
    Abstract: Provided is a storage system including: a nonvolatile memory which stores and erases data for respective blocks; and a controller for inputting and outputting the data to and from the nonvolatile memory, wherein: the storage system has a storage area including: a rewritable area where a stored data can be erased; and a write-once area where the stored data cannot be erased; and the controller determines a block belonging to the rewritable area based on an attribute of the block, and performs a wear leveling process and a reclamation process only on the block determined as belonging to the rewritable area.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: November 3, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Manabu Ishida
  • Publication number: 20090223254
    Abstract: An ankle length sock having an opening welt positioned in the vicinity of an ankle of a wearer, and having an elastic welt provided at the opening welt is provided. The sock may include a compression area with high elasticity and high compressive force disposed laterally in a diagonal direction in an area extending from behind an arch portion to an Achilles tendon portion above a heel portion. A size control course with a knitted fabric increased by 4-20 courses may be disposed between the compression area and the heel portion. An additional pocket may be interknit with 2-24 courses by reverse knitting, repeatedly alternating normal rotation and reverse rotation of the circular knitting machine cylinder, at a position on the sole portion side between the size control course and the compression area.
    Type: Application
    Filed: February 6, 2009
    Publication date: September 10, 2009
    Inventor: Manabu Ishida
  • Publication number: 20090077334
    Abstract: When a file server is to create data that does not permit falsification in an external storage, it is not possible to guarantee that the rewriting of this data can be prevented from a computer connected to the external storage without going through a file server. Provided is a storage system configured from a first storage having a file I/O processing unit and a second storage connected to this first storage, wherein the first storage includes a unit for requesting a change of access authority to the storage area in the own storage and in the second storage provided to the own storage. An access request to a storage area in a second storage from a computer connected to a second storage without going through a file I/O processing unit is restricted based on the change of access authority executed by the second storage upon receiving the request from the first storage.
    Type: Application
    Filed: November 18, 2008
    Publication date: March 19, 2009
    Inventors: Manabu Ishida, Yohsuke Ishii