Patents by Inventor Manabu Koike
Manabu Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984313Abstract: A semiconductor wafer according to an embodiment includes a support region facing a support member, an outer circumferential region positioned on an outer side of the support region, and an inner circumferential region positioned on an inner side of the support region. The outer circumferential region has a convex portion with a thickness protruded upward with respect to the inner circumferential region or a concave portion with a thickness recessed downward with respect to the inner circumferential region.Type: GrantFiled: March 28, 2022Date of Patent: May 14, 2024Assignee: Kioxia CorporationInventors: Takashi Koike, Manabu Takakuwa
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Patent number: 11955938Abstract: Proposed is an acoustic output device that obtains enough distance attenuation to achieve localization of a sound field by controlling the driving of a loudspeaker array by use of a more compact shape. The acoustic output device 10 comprises: a loudspeaker array 20 that includes a plurality of loudspeakers 20-1, 20-2, . . . , 20-N arranged in a two-dimensional plane; and an amplifier array 40 that includes a plurality of amplifiers 40-1, 40-2, . . . , 40-N that control the amplitude and phase of the drive signals for each loudspeaker according to the eigenvectors of the predetermined radiation mode of the loudspeaker array 20.Type: GrantFiled: September 11, 2020Date of Patent: April 9, 2024Assignees: The University of Tokyo, KOGAKUIN UNIVERSITY, Foster Electric Company, LimitedInventors: Tsutomu Kaizuka, Kimihiko Nakano, Yoshio Koike, Yoshiteru Uchida, Manabu Sasajima
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Patent number: 11494327Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.Type: GrantFiled: February 8, 2021Date of Patent: November 8, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Manabu Koike
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Patent number: 11455248Abstract: A semiconductor device performs a software lock-step. The semiconductor device includes a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory, a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory, a third bus connectable to a third memory, and a transfer control circuit coupled to the first to third buses. when the software lock-step is performed, the second circuit group converts an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space.Type: GrantFiled: May 6, 2020Date of Patent: September 27, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Atsushi Nakamura, Akihiro Yamamoto, Kazuaki Terashima, Manabu Koike
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Publication number: 20210349819Abstract: A semiconductor device performs a software lock-step. The semiconductor device includes a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory, a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory, a third bus connectable to a third memory, and a transfer control circuit coupled to the first to third buses. when the software lock-step is performed, the second circuit group converts an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space.Type: ApplicationFiled: May 6, 2020Publication date: November 11, 2021Inventors: Atsushi NAKAMURA, Akihiro YAMAMOTO, Kazuaki TERASHIMA, Manabu KOIKE
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Publication number: 20210165754Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.Type: ApplicationFiled: February 8, 2021Publication date: June 3, 2021Inventor: Manabu KOIKE
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Patent number: 10949369Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.Type: GrantFiled: April 13, 2020Date of Patent: March 16, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Manabu Koike
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Publication number: 20200242060Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Inventor: Manabu KOIKE
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Patent number: 10628360Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.Type: GrantFiled: November 1, 2018Date of Patent: April 21, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Manabu Koike
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Patent number: 10511799Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.Type: GrantFiled: September 17, 2018Date of Patent: December 17, 2019Assignee: Renesas Electronics CorporationInventors: Hiroyuki Hamasaki, Atsushi Nakamura, Manabu Koike, Hideaki Kido, Nobuyasu Kanekawa
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Publication number: 20190196998Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.Type: ApplicationFiled: November 1, 2018Publication date: June 27, 2019Inventor: Manabu KOIKE
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Publication number: 20190020849Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.Type: ApplicationFiled: September 17, 2018Publication date: January 17, 2019Inventors: Hiroyuki HAMASAKI, Atsushi NAKAMURA, Manabu KOIKE, Hideaki KIDO, Nobuyasu KANEKAWA
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Patent number: 10104332Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.Type: GrantFiled: April 25, 2018Date of Patent: October 16, 2018Assignee: Renesas Electronics CorporationInventors: Hiroyuki Hamasaki, Atsushi Nakamura, Manabu Koike, Hideaki Kido, Nobuyasu Kanekawa
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Publication number: 20180241964Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.Type: ApplicationFiled: April 25, 2018Publication date: August 23, 2018Inventors: Hiroyuki HAMASAKI, Atsushi NAKAMURA, Manabu KOIKE, Hideaki KIDO, Nobuyasu KANEKAWA
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Patent number: 9986196Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.Type: GrantFiled: October 11, 2016Date of Patent: May 29, 2018Assignee: Renesas Electronics CorporationInventors: Hiroyuki Hamasaki, Atsushi Nakamura, Manabu Koike, Hideaki Kido, Nobuyasu Kanekawa
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Patent number: 9978117Abstract: A semiconductor apparatus pertaining to one embodiment has: a first processor that operates by a first program and reads pixel data from a storage unit; a second processor that operates by a second program, performs processing to the pixel data, and writes the processed pixel data back to the storage unit; and a buffer circuit that transfers the pixel data from the first processor to the second processor.Type: GrantFiled: January 26, 2014Date of Patent: May 22, 2018Assignee: Renesas Electronics CorporationInventors: Manabu Koike, Akihiro Yamamoto, Atsushi Nakamura, Hideaki Kido
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Publication number: 20180039858Abstract: An image recognition apparatus 100 includes a gradient feature computation unit 120 configured to calculate, from an image divided into a plurality of blocks, gradient feature values for each of the plurality of blocks, a combination pattern storage unit 160 configured to store a plurality of combination patterns of the gradient feature values, and a co-occurrence feature computation unit 131 configured to calculate a co-occurrence feature value in a plurality of blocks for each of the plurality of combination patterns. Further, image recognition apparatus 100 includes an arithmetic computation unit 132 configured to calculate an addition value by adding the co-occurrence feature value calculated for each of the plurality of blocks for each of the plurality of combination patterns, a statistical data generation unit 140 configured to generate statistical data from the addition value.Type: ApplicationFiled: May 21, 2017Publication date: February 8, 2018Inventors: Akira UTAGAWA, Takaaki SATO, Atsushi NAKAMURA, Manabu KOIKE, Masaya ITOH
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Publication number: 20170147264Abstract: An image processing apparatus includes: a first memory that stores image data; a second memory that can be accessed at a speed higher than that in an access to the first memory; a first operation unit that executes a predetermined task on a predetermined area of the image data transferred from the first memory to the second memory; a second operation unit that determines whether there is an overlapping part of a first area of the image data executed corresponding to a first task executed by the first operation unit and a second area of the image data executed corresponding to a second task different from the first task; and a memory control apparatus that controls the first memory and the second memory. The memory control apparatus performs control to reuse the image data in the second memory when it is determined that there is an overlapping part.Type: ApplicationFiled: October 28, 2016Publication date: May 25, 2017Inventors: Motoyasu Takabatake, Hisashi Shiota, Atsushi Nakamura, Manabu Koike
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Publication number: 20170034471Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.Type: ApplicationFiled: October 11, 2016Publication date: February 2, 2017Inventors: Hiroyuki HAMASAKI, Atsushi NAKAMURA, Manabu KOIKE, Hideaki KIDO, Nobuyasu KANEKAWA
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Patent number: 9503637Abstract: An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.Type: GrantFiled: November 2, 2014Date of Patent: November 22, 2016Assignee: Renesas Electronics CorporationInventors: Hiroyuki Hamasaki, Atsushi Nakamura, Manabu Koike, Hideaki Kido, Nobuyasu Kanekawa