Patents by Inventor Manabu Matsuyama

Manabu Matsuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190377548
    Abstract: An arithmetic processing apparatus includes a memory; and a processor coupled to the memory and configured to: acquire input data and output data in each of a plurality of operations using predetermined data for an information processing including the plurality of operations of a floating-point format to, extract a specific operation represented by a complicated function including at least a transcendental function among the plurality of operations, obtain an alternative function having a smaller computation amount than the complicated function in the extracted specific operation based on the input data, and substitute the specific operation in the information processing with the alternative function.
    Type: Application
    Filed: May 2, 2019
    Publication date: December 12, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Manabu Matsuyama
  • Patent number: 8291360
    Abstract: A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: October 16, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hayato Higuchi, Shinichi Sutou, Tsuguchika Tabaru, Manabu Matsuyama, Ryuichi Ohzeki, Toshihiro Suzuki
  • Patent number: 8266416
    Abstract: A dynamic reconfiguration supporting method that generates a driver function to cause a dynamic reconfiguration circuit to execute a program of an application described in a predetermined language, includes acquiring a configuration defining file representing a configuration of a cluster of the dynamic reconfiguration circuit in execution of the process of the application, generating an address map representing an address of a processing element (to be referred to as “PE” hereinafter) in the cluster on the basis of the configuration defining file acquired by the acquiring operation, generating a driver function that associates the function and an address of the PE which executes the function with reference to the address map, when a PE which executes a function described in the application is allocated from the PE, and creating a driver function file that stores the driver function.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: September 11, 2012
    Assignee: Fujitsu Limited
    Inventors: Koji Ishihara, Tetsuo Kawano, Kyoji Sato, Tsuguchika Tabaru, Manabu Matsuyama, Ryuichi Ohzeki, Masato Kondo
  • Publication number: 20100017761
    Abstract: A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.
    Type: Application
    Filed: July 15, 2009
    Publication date: January 21, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hayato HIGUCHI, Shinichi Sutou, Tsuguchika Tabaru, Manabu Matsuyama, Ryuichi Ohzeki, Toshihiro Suzuki
  • Publication number: 20090164773
    Abstract: A dynamic reconfiguration supporting method that generates a driver function to cause a dynamic reconfiguration circuit to execute a program of an application described in a predetermined language, includes acquiring a configuration defining file representing a configuration of a cluster of the dynamic reconfiguration circuit in execution of the process of the application, generating an address map representing an address of a processing element (to be referred to as “PE” hereinafter) in the cluster on the basis of the configuration defining file acquired by the acquiring operation, generating a driver function that associates the function and an address of the PE which executes the function with reference to the address map, when a PE which executes a function described in the application is allocated from the PE, and creating a driver function file that stores the driver function.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 25, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Koji ISHIHARA, Tetsuo Kawano, Kyoji Sato, Tsuguchika Tabaru, Manabu Matsuyama, Ryuichi Ohzeki, Masato Kondo
  • Patent number: 7412696
    Abstract: The apparatus according to the present invention adds a sequence of instructions for recording a maximum of two sets of values assigned to variables in the procedure under the first execution and whose appearance frequencies can reach 50% or more and their appearance frequencies to the intermediate data of a source program to obtain primary profile information after the end of a first execution. Further it adds another sequence of instructions for recording the appearance frequencies of the values of the primary profile information and the execution frequency of the procedure to the intermediate data to obtain final profile information after the end of a second execution. Then, it calculates a value whose appearance frequency with respect to a variable is 50% or more on the basis of the final profile information to optimize the procedure regarding this value and thereby generate an object program.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: August 12, 2008
    Assignee: Fujitsu Limited
    Inventor: Manabu Matsuyama
  • Publication number: 20050050532
    Abstract: The apparatus according to the present invention adds a sequence of instructions for recording a maximum of two sets of values assigned to variables in the procedure under the first execution and whose appearance frequencies can reach 50% or more and their appearance frequencies to the intermediate data of a source program to obtain primary profile information after the end of a first execution. Further it adds another sequence of instructions for recording the appearance frequencies of the values of the primary profile information and the execution frequency of the procedure to the intermediate data to obtain final profile information after the end of a second execution. Then, it calculates a value whose appearance frequency with respect to a variable is 50% or more on the basis of the final profile information to optimize the procedure regarding this value and thereby generate an object program.
    Type: Application
    Filed: March 29, 2004
    Publication date: March 3, 2005
    Inventor: Manabu Matsuyama
  • Publication number: 20040049768
    Abstract: According to the present invention, the compiler inputs a plurality of pieces of source data composing a large-scale program on basis of an user-designated information, subjects the source data to syntax analysis, and analyzes attributes of a relation between caller (parent procedure) and callee (child procedure) in the source data from the result of the syntax analysis and registers the attribute in a data table. Then, if the the callee is not registered in the data table, the compiler marks the attributes of the caller procedure with “optimization unnecessary” and then optimizes other procedures excluding the parent procedure marked with “optimization unnecessary”.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 11, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Manabu Matsuyama, Tadashi Nakahira, Kaname Mita, Taisuke Tahara
  • Patent number: 6233732
    Abstract: A compiling system includes a first unit for converting a source program into an intermediate text formed of intermediate codes, each of the intermediate codes having a portion used to explicitly indicate information regarding a state of computer hardware, the computer hardware being operated in accordance with a machine language program, and a second unit for generating a machine language program using the intermediate codes of the intermediate text. In addition, a compiling system includes a first unit for converting a source program into an intermediate text formed of intermediate codes, each of the intermediate codes having a portion used to define a plurality of values, and a second unit for generating a machine language program using the intermediate codes of the intermediate text.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: May 15, 2001
    Assignee: Fujitsu Limited
    Inventors: Manabu Matsuyama, Yutaka Igarashi, KohIchiro Hotta, Masakazu Hayashi
  • Patent number: 5742803
    Abstract: When a flow graph is created for a program including a complex if statement, the respective branch conditions in the complex if statement are separated and the flow graph designating the control flow corresponding to the logical value of respective branch conditions are created. Next, to perform the branch probability determining/allocating process, in the above flow graph, the value corresponding to the number of executions of respective paths is calculated so that the whole branch probability of the complex if statement designated by the optimization designating statement and the branch probability of respective branch conditions is assigned to the path corresponding to respective branch conditions.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: April 21, 1998
    Assignee: Fujitsu Limited
    Inventors: Yutaka Igarashi, KohIchiro Hotta, Masakazu Hayashi, Manabu Matsuyama