Patents by Inventor Mandar B. Pandit
Mandar B. Pandit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352349Abstract: Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.Type: ApplicationFiled: July 10, 2023Publication date: November 2, 2023Applicant: Applied Materials, Inc.Inventors: Mandar B. Pandit, Man-Ping Cai, Wenhui Li, Michael Wenyoung Tsiang, Praket Prakash Jha, Jingmin Leng
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Patent number: 11699623Abstract: Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.Type: GrantFiled: October 14, 2020Date of Patent: July 11, 2023Assignee: Applied Materials, Inc.Inventors: Mandar B. Pandit, Man-Ping Cai, Wenhui Li, Michael Wenyoung Tsiang, Praket Prakash Jha, Jingmin Leng
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Publication number: 20220375747Abstract: Processing methods disclosed herein comprise forming a nucleation layer and a flowable chemical vapor deposition (FCVD) film on a substrate surface by exposing the substrate surface to a silicon-containing precursor and a reactant. By controlling at least one of a precursor/reactant pressure ratio, a precursor/reactant flow ratio and substrate temperature formation of miniature defects is minimized. Controlling at least one of the process parameters may reduce the number of miniature defects. The FCVD film can be cured by any suitable curing process to form a smooth FCVD film.Type: ApplicationFiled: May 20, 2021Publication date: November 24, 2022Applicant: Applied Materials, Inc.Inventors: Wenhui Li, Praket P. Jha, Mandar B. Pandit, Man-Ping Cai, Jingmei Liang, Michael Wenyoung Tsiang
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Publication number: 20220115275Abstract: Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.Type: ApplicationFiled: October 14, 2020Publication date: April 14, 2022Applicant: Applied Materials, Inc.Inventors: Mandar B. Pandit, Man-Ping Cai, Wenhui Li, Michael Wenyoung Tsiang, Praket Prakash Jha, Jingmin Leng
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Publication number: 20200043734Abstract: Methods may be performed to limit footing, pitch walking, and other alignment issues. The methods may include forming a treatment gas plasma within a processing region of a semiconductor processing chamber. The methods may further include directing effluents of the treatment gas plasma towards a semiconductor substrate within the processing region of the semiconductor processing chamber, and anisotropically modifying a surface of a first material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may also include passivating a surface of a second material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may further include forming a remote fluorine-containing plasma to produce fluorine-containing plasma effluents, and flowing the fluorine-containing plasma effluents to the processing region of the semiconductor processing chamber.Type: ApplicationFiled: October 11, 2019Publication date: February 6, 2020Applicant: Applied Materials, Inc.Inventors: Mandar B. Pandit, Mang-Mang Ling, Tom Choi, Nitin K. Ingle
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Patent number: 10490406Abstract: Methods may be performed to limit footing, pitch walking, and other alignment issues. The methods may include forming a treatment gas plasma within a processing region of a semiconductor processing chamber. The methods may further include directing effluents of the treatment gas plasma towards a semiconductor substrate within the processing region of the semiconductor processing chamber, and anisotropically modifying a surface of a first material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may also include passivating a surface of a second material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may further include forming a remote fluorine-containing plasma to produce fluorine-containing plasma effluents, and flowing the fluorine-containing plasma effluents to the processing region of the semiconductor processing chamber.Type: GrantFiled: April 10, 2018Date of Patent: November 26, 2019Assignee: Appled Materials, Inc.Inventors: Mandar B. Pandit, Mang-Mang Ling, Tom Choi, Nitin K. Ingle
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Publication number: 20190311900Abstract: Methods may be performed to limit footing, pitch walking, and other alignment issues. The methods may include forming a treatment gas plasma within a processing region of a semiconductor processing chamber. The methods may further include directing effluents of the treatment gas plasma towards a semiconductor substrate within the processing region of the semiconductor processing chamber, and anisotropically modifying a surface of a first material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may also include passivating a surface of a second material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may further include forming a remote fluorine-containing plasma to produce fluorine-containing plasma effluents, and flowing the fluorine-containing plasma effluents to the processing region of the semiconductor processing chamber.Type: ApplicationFiled: April 10, 2018Publication date: October 10, 2019Applicant: Applied Materials, Inc.Inventors: Mandar B. Pandit, Mang-Mang Ling, Tom Choi, Nitin K. Ingle
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Patent number: 10373822Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.Type: GrantFiled: November 17, 2017Date of Patent: August 6, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Prashant Kumar Kulshreshtha, Sudha Rathi, Praket P. Jha, Saptarshi Basu, Kwangduk Douglas Lee, Martin J. Seamons, Bok Hoen Kim, Ganesh Balasubramanian, Ziqing Duan, Lei Jing, Mandar B. Pandit
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Patent number: 10354889Abstract: Processing methods may be performed to limit damage of features of a substrate, such as missing fin damage. The methods may include forming a plasma of an inert precursor within a processing region of a processing chamber. Effluents of the plasma of the inert precursor may be utilized to passivate an exposed region of an oxygen-containing material that extends about a feature formed on a semiconductor substrate. A plasma of a hydrogen-containing precursor may also be formed within the processing region. Effluents of the plasma of the hydrogen-containing precursor may be directed, with DC bias, towards an exposed silicon-containing material on the semiconductor substrate. The methods may also include anisotropically etching the exposed silicon-containing material with the plasma effluents of the hydrogen-containing precursor, where the plasma effluents of the hydrogen-containing precursor selectively etch silicon relative to silicon oxide.Type: GrantFiled: July 17, 2017Date of Patent: July 16, 2019Assignee: Applied Materials, Inc.Inventors: Tom Choi, Mandar B. Pandit, Mang-Mang Ling, Nitin K. Ingle
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Publication number: 20190019690Abstract: Processing methods may be performed to limit damage of features of a substrate, such as missing fin damage. The methods may include forming a plasma of an inert precursor within a processing region of a processing chamber. Effluents of the plasma of the inert precursor may be utilized to passivate an exposed region of an oxygen-containing material that extends about a feature formed on a semiconductor substrate. A plasma of a hydrogen-containing precursor may also be formed within the processing region. Effluents of the plasma of the hydrogen-containing precursor may be directed, with DC bias, towards an exposed silicon-containing material on the semiconductor substrate. The methods may also include anisotropically etching the exposed silicon-containing material with the plasma effluents of the hydrogen-containing precursor, where the plasma effluents of the hydrogen-containing precursor selectively etch silicon relative to silicon oxide.Type: ApplicationFiled: July 17, 2017Publication date: January 17, 2019Applicant: Applied Materials, Inc.Inventors: Tom Choi, Mandar B. Pandit, Mang-Mang Ling, Nitin K. Ingle
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Patent number: 10074534Abstract: Embodiments of the disclosure relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, generating a plasma in the processing chamber at a deposition temperature of about 80° C. to about 550° C. to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers, and removing the patterned features formed from the sacrificial dielectric layer.Type: GrantFiled: June 28, 2017Date of Patent: September 11, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Swayambhu P. Behera, Shahid Shaikh, Pramit Manna, Mandar B. Pandit, Tersem Summan, Patrick Reilly, Deenesh Padhi, Bok Hoen Kim, Heung Lak Park, Derek R. Witty
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Publication number: 20180096843Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.Type: ApplicationFiled: November 17, 2017Publication date: April 5, 2018Inventors: Prashant Kumar Kulshreshtha, Sudha Rathi, Praket P. Jha, Saptarshi Basu, Kwangduk Douglas Lee, Martin J. Seamons, Bok Hoen Kim, Ganesh Balasubramanian, Ziqing Duan, Lei Jing, Mandar B. Pandit
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Patent number: 9837265Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.Type: GrantFiled: June 24, 2016Date of Patent: December 5, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Prashant Kumar Kulshreshtha, Sudha Rathi, Praket P. Jha, Saptarshi Basu, Kwangduk Douglas Lee, Martin J. Seamons, Bok Hoen Kim, Ganesh Balasubramanian, Ziqing Duan, Lei Jing, Mandar B. Pandit
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Publication number: 20170301537Abstract: Embodiments of the disclosure relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, generating a plasma in the processing chamber at a deposition temperature of about 80° C. to about 550° C. to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers, and removing the patterned features formed from the sacrificial dielectric layer.Type: ApplicationFiled: June 28, 2017Publication date: October 19, 2017Inventors: Swayambhu P. BEHERA, Shahid SHAIKH, Pramit MANNA, Mandar B. PANDIT, Tersem SUMMAN, Patrick REILLY, Deenesh PADHI, Bok Hoen KIM, Heung Lak PARK, Derek R. WITTY
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Patent number: 9721784Abstract: Embodiments of the invention relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer with a predetermined thickness over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, wherein a volumetric flow rate of hydrocarbon source:plasma-initiating gas:dilution gas is in a ratio of 1:0.5:20, generating a plasma at a deposition temperature of about 300 C to about 500 C to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate, and removing the patterned features.Type: GrantFiled: February 14, 2014Date of Patent: August 1, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Swayambhu P. Behera, Shahid Shaikh, Pramit Manna, Mandar B. Pandit, Tersem Summan, Patrick Reilly, Deenesh Padhi, Bok Hoen Kim, Heung Lak Park, Derek R. Witty
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Publication number: 20160307752Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Prashant Kumar KULSHRESHTHA, Sudha RATHI, Praket P. JHA, Saptarshi BASU, Kwangduk Douglas LEE, Martin J. SEAMONS, Bok Hoen KIM, Ganesh BALASUBRAMANIAN, Ziqing DUAN, Lei JING, Mandar B. PANDIT
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Patent number: 9390910Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.Type: GrantFiled: November 20, 2014Date of Patent: July 12, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Prashant Kumar Kulshreshtha, Sudha Rathi, Praket P. Jha, Saptarshi Basu, Kwangduk Douglas Lee, Martin J. Seamons, Bok Hoen Kim, Ganesh Balasubramanian, Ziqing Duan, Lei Jing, Mandar B. Pandit
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Patent number: 9343272Abstract: Methods of forming self-aligned structures on patterned substrates are described. The methods may be used to form metal lines or vias without the use of a separate photolithography pattern definition operation. Self-aligned contacts may be produced regardless of the presence of spacer elements. The methods include directionally ion-implanting a gapfill portion of a gapfill silicon oxide layer to implant into the gapfill portion without substantially ion-implanting the remainder of the gapfill silicon oxide layer (the sidewalls). Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the patterned substrate such that the gapfill portions of silicon oxide are selectively etched relative to other exposed portions exposed parallel to the ion implantation direction. Without ion implantation, the etch operation would be isotropic owing to the remote nature of the plasma excitation during the etch process.Type: GrantFiled: January 8, 2015Date of Patent: May 17, 2016Assignee: Applied Materials, Inc.Inventors: Mandar B. Pandit, Anchuan Wang, Nitin K. Ingle
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Patent number: 9337314Abstract: A method to selectively process a three dimensional device, comprising providing a substrate having a first surface that extends horizontally, the substrate comprising a structure containing a second surface that extends vertically from the first surface; providing a film on the substrate, the film comprising carbon species; and etching a selected portion of the film by exposing the selected portion of the film to an etchant containing hydrogen species, where the etchant excludes oxygen species and fluorine species.Type: GrantFiled: December 11, 2013Date of Patent: May 10, 2016Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Nilay A. Pradhan, Benjamin Colombeau, Naushad K. Variam, Mandar B. Pandit, Christopher Dennis Bencher, Adam Brand
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Publication number: 20160099147Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.Type: ApplicationFiled: November 20, 2014Publication date: April 7, 2016Inventors: Prashant Kumar KULSHRESHTHA, Sudha RATHI, Praket P. JHA, Saptarshi BASU, Kwangduk Douglas LEE, Martin J. SEAMONS, Bok Hoen KIM, Ganesh BALASUBRAMANIAN, Ziqing DUAN, Lei JING, Mandar B. PANDIT