Abstract: The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate, at the bottoms of which in each case a first conductive region is provided, at the peaks of which in each case a second conductive region of the same conduction type as the first conductive region is provided, and in the walls of which in each case an intermediately located channel region is 0 provided; and having word lines which extend in the transverse direction along the main face of the semiconductor substrate, through specific bit-line trenches, to activate transistors provided there. An additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.

Abstract: An integrated semiconductor circuit, such as an A/D converter, includes a first zone having capacitors disposed therein. The capacitors have capacitor plates being formed of a first conductive layer and a second conductive layer. A second zone has circuit elements disposed therein. A planarizing layer and a cover layer insulate the first and second conductive layers from one another in the second zone, except for a possible peripheral region. A dielectric is formed only of the cover layer between the capacitor plates in the first zone, except for a possible peripheral region.

Abstract: The memory cell configuration has a multiplicity of preferably ferroelectric memory cells in a semiconductor substrate. Mutually parallel bit line trenches run in the longitudinal direction in the main surface of the semiconductor substrate. Bit lines are disposed in the bottoms of the trenches. Source/drain regions are formed in the crowns of the trenches. Channel regions are provided in the walls of the trenches. The channel region on a wall in each case is configured such that a drivable selection transistor of the relevant memory cell is formed there, while the channel region on the other wall is configured such that the transistor located there is closed. Insulated word lines for driving the selection transistors run in the transverse direction along the main surface of the semiconductor substrate through the bit line trenches.

Abstract: An integrated semiconductor circuit, such as an A/D converter, includes a first zone having capacitors disposed therein. The capacitors have capacitor plates being formed of a first conductive layer and a second conductive layer. A second zone has circuit elements disposed therein. A planarizing layer and a cover layer insulate the first and second conductive layers from one another in the second zone, except for a possible peripheral region. A dielectric is formed only of the cover layer between the capacitor plates in the first zone, except for a possible peripheral region.

Abstract: Aluminiferous structures having a sidewall angle greater than or equal to zero are produced by the addition of a volatile hydrocarbon to the etching gas mixture in a plasma etching process. The volatile hydrocarbon promotes the sidewall passivation, so that extremely fine structures can be anisotropically etched. Given aluminum-copper alloys, moreover, the formation of etching residues that contain copper and are not easily volatilized is also prevented.