Abstract: By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.

Abstract: By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers with high tensile stress may be commonly formed on PMOS and NMOS transistors, wherein a deleterious effect on the PMOS transistor may be compensated for by a corresponding compressively stressed contact etch stop layer, while the NMOS transistor comprises a contact etch stop layer with tensile stress. Furthermore, the PMOS transistor comprises an embedded strained semiconductor layer for efficiently creating compressive strain in the channel region.

Abstract: By providing an asymmetric design of a halo region and extension regions of a field effect transistor, the transistor performance may significantly be enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even completely be avoided, wherein a moderately reduced concentration gradient may further enhance the transistor performance.

Abstract: Polysilicon lines are formed, featuring an upper portion extending beyond the lower portion that defines the required CD. Accordingly, metal silicide layers of increased dimensions can be formed on the upper portion of the polysilicon lines so that the resulting gate structures exhibit a very low final sheet resistance. Moreover, in situ sidewall spacers are realized during the process for forming the polysilicon lines and without additional steps and/or costs.

Abstract: In a method for fabricating a semiconductor device different types of a metal-semiconductor compound are formed on or in at least two different conductive semiconductor regions so that for each semiconductor region the metal-semiconductor compound region may be formed to obtain an optimum overall performance of the semiconductor device. On one of the two semiconductor regions, the metal-semiconductor compound is formed of at least two different metal layers, whereas the metal-semiconductor compound in or on the other semiconductor region is formed from a single metal layer.

Abstract: The present invention provides a technique for forming a metal silicide, such as a cobalt disilicide, even at extremely scaled device dimensions without unduly degrading the film integrity of the metal silicide. To this end, an ion implantation may be performed, advantageously with silicon, prior to a final anneal cycle, thereby correspondingly modifying the grain structure of the precursor of the metal silicide.

Abstract: By using an implantation technique for forming a buried insulation layer, an SOI-type configuration may be achieved for hybrid orientation substrates, thereby significantly enhancing the further fabrication processes in forming circuit elements on differently oriented semiconductor regions. Consequently, process complexity for methodology and production steps is significantly reduced compared to fabrication processes based on conventional hybrid orientation substrates.

Abstract: A semiconductor device comprises an isolation trench and a contact trench that may contact a buried conductive region. The contact trench comprises insulating sidewall spacers that are formed during the filling of the isolation trench with an insulating material and the subsequent anisotropic etching of the excess material. Thereafter, the contact trench is filled with a conductive material. Thus, the formation of a contact for a buried region may be carried out simultaneously with the formation of a trench isolation structure, thereby minimizing the number of process steps required.

Abstract: SRAM devices utilizing tensile-stressed strain films and methods for fabricating such SRAM devices are provided. An SRAM device, in one embodiment, comprises an NFET and a PFET that are electrically coupled and physically isolated. The PFET has a gate region, a source region, and a drain region. A tensile-strained stress film is disposed on the gate region and at least a portion of the source region and the drain region of the PFET. A method for fabricating a cell of an SRAM device comprises fabricating an NFET and a PFET overlying a substrate. The PFET and the NFET are electically coupled and are physically isolated. A tensile-strained stress film is deposited on the gate region and at least a portion of the source region and the drain region of the PFET.

Abstract: By direct bonding of two crystalline semiconductor layers of different crystallographic orientation and/or material composition and/or internal strain, bulk-like hybrid substrates may be formed, thereby providing the potential for forming semiconductor devices in accordance with a single transistor architecture on the hybrid substrate.

Abstract: A method for improving the etch behavior of disposable features in the fabrication of a semiconductor device is disclosed. The semiconductor device comprises a bottom anti-reflective coating layer and/or a disposable sidewall spacer which are to be removed in a subsequent etch removal process. The bottom anti-reflective coating layer and/or the disposable sidewall spacer are irradiated by heavy inert ions to alter the structure of the irradiated features and to increase concurrently the etch rate of the employed materials, for example, silicon nitride or silicon reacted nitride.

Abstract: By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate electrodes of CMOS devices subsequently formed in the layer of gate material. The improved uniformity of the dopant distribution results in reduced gate depletion and reduced threshold voltage shift in the transistors of the CMOS devices.

Abstract: By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted. In particular, in in-laid gate structure transistor architecture, NMOS transistors and PMOS transistors may receive a tensile and a compressive stress, respectively.

Abstract: By providing an asymmetric design of a halo region and extension regions of a field effect transistor, the transistor performance may significantly be enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even completely be avoided, wherein a moderately reduced concentration gradient may further enhance the transistor performance.

Abstract: A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.

Abstract: By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

Abstract: By providing a test structure including a plurality of test pads, the anisotropic behavior of stress and strain influenced electrical characteristics, such as the electron mobility, may be determined in a highly efficient manner. Moreover, the test pads may enable the detection of stress and strain induced modifications with a spatial resolution in the order of magnitude of individual circuit elements.

Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.

Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

Abstract: In an SOI diode structure, the conventional transistor-like MOS configuration is eliminated by replacing the polysilicon line by a completely dielectric region. This region may be used as an implantation mask to control a dopant gradient of a PN-junction that forms below the dielectric region. Moreover, during the salicide process, the dielectric region prevents the PN-junction from being shorted. Thus, a depletion of the active region caused by the MOS structure may be avoided. Therefore, the functioning of the PN-junction is maintained even for extremely thin semiconductor layers.