Patents by Inventor Manfred Ramin
Manfred Ramin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140315377Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.Type: ApplicationFiled: July 1, 2014Publication date: October 23, 2014Inventors: Manfred Ramin, Michael F. Pas, Husam N. Alshareef
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Patent number: 8802519Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.Type: GrantFiled: April 2, 2013Date of Patent: August 12, 2014Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael F. Pas, Husam N. Alshareef
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Patent number: 8748246Abstract: A transistor includes a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. An independent work function adjustment process implants Group IIIa series dopants into a gate polysilicon layer of a PMOS transistor and implants lanthanide series dopants into a gate polysilicon layer of a NMOS transistor.Type: GrantFiled: December 10, 2010Date of Patent: June 10, 2014Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael Pas
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Patent number: 8409943Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.Type: GrantFiled: December 28, 2010Date of Patent: April 2, 2013Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
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Patent number: 8304333Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.Type: GrantFiled: September 21, 2010Date of Patent: November 6, 2012Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
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Patent number: 8304342Abstract: A chemical mechanical polishing (CMP) stop layer is implemented in a semiconductor fabrication process. The CMP stop layer, among other things, mitigates erosion of sidewall spacers during semiconductor fabrication and adverse effects associated therewith.Type: GrantFiled: October 31, 2006Date of Patent: November 6, 2012Assignee: Texas Instruments IncorporatedInventors: Michael Francis Pas, Manfred Ramin
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Patent number: 8043947Abstract: A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect.Type: GrantFiled: November 16, 2007Date of Patent: October 25, 2011Assignee: Texas Instruments IncorporatedInventors: Angelo Pinto, Weize Xiong, Manfred Ramin
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Publication number: 20110223754Abstract: A transistor includes a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. An independent work function adjustment process implants Group Ma series dopants into a gate polysilicon layer of a PMOS transistor and implants lanthanide series dopants into a gate polysilicon layer of a NMOS transistor.Type: ApplicationFiled: December 10, 2010Publication date: September 15, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Manfred Ramin, Michael Pas
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Publication number: 20110223757Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.Type: ApplicationFiled: December 28, 2010Publication date: September 15, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
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Publication number: 20110006375Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.Type: ApplicationFiled: September 21, 2010Publication date: January 13, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
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Patent number: 7858459Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.Type: GrantFiled: April 20, 2007Date of Patent: December 28, 2010Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
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Patent number: 7807522Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal nitride is formed above a gate dielectric. A lanthaide series metal is implanted into the metal screen layer above the gate dielectric. The lanthaide metal is contained in the screen layer or at the interface between the screen metal layer and the gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.Type: GrantFiled: January 31, 2007Date of Patent: October 5, 2010Assignee: Texas Instruments IncorporatedInventors: Husam Alshareef, Manfred Ramin, Michael F. Pas
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Patent number: 7799669Abstract: A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer.Type: GrantFiled: April 27, 2007Date of Patent: September 21, 2010Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
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Patent number: 7737015Abstract: A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transistor, oxidizing a portion of the S/D silicide to form an oxide barrier overlying the S/D silicide in the source/drain regions, removing the nitride hardmask from the polysilicon gate, and forming a gate silicide such as by deposition of a gate silicide metal over the polysilicon gate and the oxide barrier in the source/drain regions to form a fully silicided (FUSI) gate in the transistor. Thus, the oxide barrier protects the source/drain regions from additional silicide formation by the gate silicide metal formed thereafter. The method may further comprise selectively removing the oxide barrier in the source/drain regions after forming the fully silicided (FUSI) gate.Type: GrantFiled: February 27, 2007Date of Patent: June 15, 2010Assignee: Texas Instruments IncorporatedInventors: Puneet Kohli, Craig Huffman, Manfred Ramin
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Patent number: 7629212Abstract: A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body, forming a work function adjusting layer on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer above the work function adjusting material in the PMOS region, depositing a tungsten germanium gate electrode layer above the gate dielectric in the NMOS region annealing the semiconductor device, depositing a metal nitride barrier layer on the tungsten germanium layer, depositing a polysilicon layer over the metal nitride, patterning the polysilicon layer, the metal nitride layer, the tungsten germanium layer, work function adjusting layer and the gate dielectric layer to form a gate structure, and forming a source/drain on opposite sides of the gate structure.Type: GrantFiled: March 19, 2007Date of Patent: December 8, 2009Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Mark R. Visokay, Michael Francis Pas
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Publication number: 20090130817Abstract: A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation, a second crystal orientation, and a border region disposed between the first and second crystal orientations. The border region further has a defect associated with an interface of the first crystal orientation and second the second crystal orientation, wherein the defect generally extends a distance into the semiconductor body from a surface of the body. A sacrificial portion of the semiconductor body is removed from the surface thereof, wherein removing the sacrificial portion at least partially removes the defect. The sacrificial portion can be defined by oxidizing the surface at low temperature, wherein the oxidation at least partially consumes the defect. The sacrificial portion can also be removed by CMP. An STI feature may be further formed over the defect after removal of the sacrificial portion, therein consuming any remaining defect.Type: ApplicationFiled: November 16, 2007Publication date: May 21, 2009Inventors: Angelo Pinto, Weize Xiong, Manfred Ramin
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Publication number: 20090039439Abstract: A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. The method includes an independent work function adjustment process that implants Group IIIa series dopants into a gate polysilicon layer of a PMOS transistor and implants Lanthanide series dopants into a gate polysilicon layer of NMOS.Type: ApplicationFiled: October 21, 2008Publication date: February 12, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Manfred Ramin, Michael Pas
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Publication number: 20080274598Abstract: A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body, forming a work function adjusting layer on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer above the work function adjusting material in the PMOS region, depositing a tungsten germanium gate electrode layer above the gate dielectric in the NMOS region annealing the semiconductor device, depositing a metal nitride barrier layer on the tungsten germanium layer, depositing a polysilicon layer over the metal nitride, patterning the polysilicon layer, the metal nitride layer, the tungsten germanium layer, work function adjusting layer and the gate dielectric layer to form a gate structure, and forming a source/drain on opposite sides of the gate structure.Type: ApplicationFiled: March 19, 2007Publication date: November 6, 2008Inventors: Manfred Ramin, Mark R. Visokay, Michael Francis Pas
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Publication number: 20080265336Abstract: A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer.Type: ApplicationFiled: April 27, 2007Publication date: October 30, 2008Applicant: Texas Instruments IncorporatedInventors: Manfred Ramin, Michael F. Pas, Husam Alshareef
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Publication number: 20080261368Abstract: Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Inventors: Manfred Ramin, Michael F. Pas, Husam Alshareef