Abstract: A digital processing device comprising a plurality of parallel processing units each coupled in parallel with one another. Each of the plurality of parallel processing units comprises at least one data memory storage unit; at least one input register coupled to the at least one data memory storage unit; and an arithmetic unit coupled to the at least one input register and configured to have synchronous command processing. A program execution control unit is coupled to each of the plurality of processing units and configured such that no processing clocks are required for synchronization of data transfer from the plurality of parallel processing units. At least one data bus is coupled to the at least one input register in each of the plurality of parallel processing units.

Abstract: A method and apparatus to permute a given set of elements utilizing a permutation network which uses nodes and edges. The permutation network is a minimal network where each of the nodes except the input nodes has N+1 inputs and each of the nodes except the output nodes has N+1 outputs. Generation of any permutation of the provided input elements is allowed; permutations can even comprise copies of elements if desired. The network is characterized that for each output element at least two paths through the network to each input element exist and that each node can only process one element at a time.