Patents by Inventor Mangal Prasad
Mangal Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10892743Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: February 25, 2019Date of Patent: January 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 10396769Abstract: Various clock frequency dividers are disclosed. Each frequency divider includes cascaded flip-flops and a feedback logic gate. First data inputs of the flip-flops are for propagating logic values along the cascaded flip-flops and the feedback gate for generating valid states of a sequence in response to a clock signal. Each frequency divider includes an invalid state elimination circuit configured to detect an invalid state at the outputs of the flip-flops and change it into a valid state in response to the clock signal. In some implementations, the invalid state elimination circuit includes a NOR gate to detect an all-zero invalid state and generate a control signal to cause the flip-flops to output logic values associated with a valid state or to cause a multiplexer to introduce a logic value associated with a valid state. In other implementations, the invalid state elimination circuit instead includes an AND gate to detect an all-ones invalid state.Type: GrantFiled: October 18, 2017Date of Patent: August 27, 2019Assignee: QUALCOMM IncorporatedInventors: Mangal Prasad, Victor Git-Han Moy, Xiaobin Yuan, Anirban Banerjee
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Publication number: 20190190506Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: ApplicationFiled: February 25, 2019Publication date: June 20, 2019Inventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 10291217Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: March 13, 2017Date of Patent: May 14, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Publication number: 20190115908Abstract: Various clock frequency dividers are disclosed. Each frequency divider includes cascaded flip-flops and a feedback logic gate. First data inputs of the flip-flops are for propagating logic values along the cascaded flip-flops and the feedback gate for generating valid states of a sequence in response to a clock signal. Each frequency divider includes an invalid state elimination circuit configured to detect an invalid state at the outputs of the flip-flops and change it into a valid state in response to the clock signal. In some implementations, the invalid state elimination circuit includes a NOR gate to detect an all-zero invalid state and generate a control signal to cause the flip-flops to output logic values associated with a valid state or to cause a multiplexer to introduce a logic value associated with a valid state. In other implementations, the invalid state elimination circuit instead includes an AND gate to detect an all-ones invalid state.Type: ApplicationFiled: October 18, 2017Publication date: April 18, 2019Inventors: Mangal Prasad, Victor Git-Han Moy, Xiaobin Yuan, Anirban Banerjee
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Patent number: 10038468Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: GrantFiled: August 8, 2017Date of Patent: July 31, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
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Patent number: 10027297Abstract: One aspect of the present disclosure relates to a method for operating an amplifier, the amplifier including a variable resistor coupled between a source of a first input transistor and a source of a second input transistors, and a variable capacitor coupled between the source of the first input transistor and the source of the second input transistor. The method includes adjusting a resistance of the variable resistor to adjust a low-frequency gain of the amplifier, and adjusting a capacitance of the variable capacitor in an opposite direction as the adjustment to the resistance of the variable resistor.Type: GrantFiled: September 16, 2016Date of Patent: July 17, 2018Assignee: QUALCOMM IncorporatedInventors: Xiaobin Yuan, Jacob Lee Dahle, Mangal Prasad, Joseph Natonio
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Publication number: 20180083584Abstract: One aspect of the present disclosure relates to a method for operating an amplifier, the amplifier including a variable resistor coupled between a source of a first input transistor and a source of a second input transistors, and a variable capacitor coupled between the source of the first input transistor and the source of the second input transistor. The method includes adjusting a resistance of the variable resistor to adjust a low-frequency gain of the amplifier, and adjusting a capacitance of the variable capacitor in an opposite direction as the adjustment to the resistance of the variable resistor.Type: ApplicationFiled: September 16, 2016Publication date: March 22, 2018Inventors: Xiaobin Yuan, Jacob Lee Dahle, Mangal Prasad, Joseph Natonio
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Publication number: 20170331510Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: ApplicationFiled: August 8, 2017Publication date: November 16, 2017Inventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
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Patent number: 9755599Abstract: In one implementation, an amplifier comprises a load circuit comprising a plurality of inductor cells, and a drive circuit configured to receive an input signal, and to drive the load circuit based on the input signal to generate an amplified signal. The amplifier also comprises a controller configured to tune a peaking gain of the amplifier by adjusting a number of the inductor cells that are enabled.Type: GrantFiled: September 17, 2015Date of Patent: September 5, 2017Assignee: QUALCOMM IncorporatedInventors: Xiaobin Yuan, Mangal Prasad, Joseph Natonio
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Patent number: 9748927Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: GrantFiled: September 8, 2016Date of Patent: August 29, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
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Patent number: 9712144Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: September 3, 2015Date of Patent: July 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Publication number: 20170187363Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 9680418Abstract: A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.Type: GrantFiled: November 13, 2015Date of Patent: June 13, 2017Assignee: QUALCOMM IncorporatedInventors: Xiaobin Yuan, Joseph Natonio, Kevin Robert Bartholomew, Mangal Prasad
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Publication number: 20170141735Abstract: A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.Type: ApplicationFiled: November 13, 2015Publication date: May 18, 2017Inventors: Xiaobin Yuan, Joseph Natonio, Kevin Robert Bartholomew, Mangal Prasad
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Patent number: 9647618Abstract: The disclosure relates to a system and method for controlling a common mode voltage of an output differential signal of a differential signal processing circuit using a replica circuit and feedback control. The differential signal processing circuit includes two load devices, two input transistors, and two current-source transistors coupled in series between voltage rails, respectively. The replica circuit includes replica load device, replica input transistor, and replica current-source transistor coupled in series between the voltage rails. The common mode voltage of the input differential signal is applied to the replica input transistor to generate a replica output common mode voltage. A feedback circuit generates a bias voltage for the replica current-source transistor and the current-source transistors of the differential circuit to set and control the replica output common mode voltage and the output common mode voltage of the differential signal processing circuit to a target common mode voltage.Type: GrantFiled: March 30, 2016Date of Patent: May 9, 2017Assignee: QUALCOMM IncorporatedInventors: Xiaobin Yuan, Joseph Natonio, Mangal Prasad, Todd Morgan Rasmus
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Patent number: 9628059Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: June 18, 2015Date of Patent: April 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 9608610Abstract: A circuit for controlling a clock signal may include a voltage source that provides a bias voltage, and at least one delay element having a non-linear capacitive load coupled to an output of the delay element. The non-linear capacitive load receives the bias from the voltage source and controls a delay magnitude applied to a plurality of pulses of the clock signal by the delay element. Based on the bias having a first scaled voltage, the delay magnitude that is applied to the plurality of clock pulses is increased in order to generate a frequency correction to the operating frequency of a microprocessor based on a variation to a microprocessor supply voltage. Based on the bias having a second scaled voltage, the delay magnitude that is applied to the clock pulses is maintained to retain the operating frequency of the clock during the variation to the supply voltage.Type: GrantFiled: September 11, 2015Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Mangal Prasad, Marshall D. Tiner, Xiaobin Yuan
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Publication number: 20170085239Abstract: In one implementation, an amplifier comprises a load circuit comprising a plurality of inductor cells, and a drive circuit configured to receive an input signal, and to drive the load circuit based on the input signal to generate an amplified signal. The amplifier also comprises a controller configured to tune a peaking gain of the amplifier by adjusting a number of the inductor cells that are enabled.Type: ApplicationFiled: September 17, 2015Publication date: March 23, 2017Inventors: Xiaobin Yuan, Mangal Prasad, Joseph Natonio
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Patent number: 9577607Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: GrantFiled: August 3, 2015Date of Patent: February 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier Andrea Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan