Abstract: Some novel features pertain to a memory controller that includes a memory controller logic, a built-in-self-tester (BIST) logic, and a switch. The memory controller logic is for controlling memory on a memory die. The built-in-self tester (BIST) logic is for testing the memory. The switch is coupled to the BIST logic and the memory. In some implementations, the BIST logic bypasses the memory controller logic when testing the memory by accessing the memory through the switch. The switch may be controlled by the BIST logic. In some implementations, the switch is coupled to the memory controller logic. The switch may control data to the memory that is transmitted from the memory controller logic and the BIST logic based on priority of the data.

Abstract: Bed Bugs Cimicidae (referred to as bedbugs) are small parasitic insect. The name “bed bug” is derived from the incest's preferred habitat of houses and especially beds. The most common type is Cimex Lectularius, species that prefer to feed on human blood or the blood of warm-blooded animals. There are numerous health effects due to bed bug. These include skin rashes and allergic symptoms. These nocturnal insects can feed unnoticed on their hosts. Vetiver Chrysopogon zizanioides, commonly known as Vetiver, is a perennial grass of the Poaceae family, native to India. In western and northern India, it is popularly known as khus. This grass is known to grow up to 1.5 meters high and forms clumps as wide. Vetiver oil can be extracted from Vetiver roots. Normally, Vetiver is commonly used for cattle feed, aromatherapy, perfumes, soil erosion protection, ropes and handicrafts.

Abstract: A user correlation system uses aggregated data and matching/comparison in order to assign an association score that determines likelihood that unique identifiers are associated with the same user.

Abstract: A computer-implemented method for updating multiple data records in a database in a single transaction. The method includes searching a data model associated with the data records in the database for fields related to an objective. Once complete, a user will enter new objective values associated with the objective. The processor then performs a business rule validation of the fields found during the searching step with the new objective values entered. The report is then displayed to a user on a display. The user reviews the report and may approve the new objective values. If approved, the finalized objective values are applied to the database.

Abstract: This patent covers the any use of vetiver roots material to provide shade, cooling and humidifying effect to any indoor or outdoor area. The use of vetiver root material could be in form of a mat, carpet or rug, however, not limited to them in their use to provide cooling and humidifying effect. A wet or dry mat using vetiver roots is placed in path of any natural or forced air to cool the air that is passing through. The air may be naturally flowing or forced via fan through the mat to provide cooling effect as well as cleaning effect. The patent also covers the use of water with the vetiver mat to provide additional cooling and humidity. The solution significantly reduces energy consumption.

Abstract: Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented memory. During that cycle, the processor determines whether a memory segment base is zero. If the segment base is zero, the processor can access a memory location at the effective address without adding the segment base. If the segment base is not zero, such as when executing legacy code, the processor consumes another cycle to add the segment base to the effective address. Similarly, the processor consumes another cycle if the effective address or the linear address is misaligned. An integer execution unit that performs the three-operand add using a carry-save adder coupled to a carry look-ahead adder. If the segment base is not zero, the effective address is fed back through the integer execution unit to add the segment base.

Abstract: A microprocessor capable of decoding a plurality of instructions associated with a plurality of threads is disclosed. The microprocessor may comprise a first array comprising a first plurality of microcode operations associated with an instruction from within the plurality of instructions, the first array capable of delivering a first predetermined number of microcode operations from the first plurality of microcode operations. The microprocessor may further comprise a second array comprising a second plurality of microcode operations, the second array capable of providing one or more of the second plurality of microcode operations in the event that the instruction decodes into more than the first predetermined number of microcode operations. The microprocessor may further comprise an arbiter coupled between the first and second arrays, where the arbiter may determine which thread from the plurality of threads accesses the second array.

Abstract: A user correlation system uses aggregated data and matching/comparison in order to assign an association score that determines likelihood that unique identifiers are associated with the same user.

Abstract: A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.

Abstract: A multithreaded processor with a banked cache is provided. The instruction set includes at least one atomic operation which is executed in the L2 cache if the atomic memory address source data is aligned. The core executing the instruction determines whether the atomic memory address source data is aligned. If it is aligned, the atomic memory address is sent to the bank that contains the atomic memory address source data, and the operation is executed in the bank. In one embodiment, if the instruction is mis-aligned, the operation is executed in the core.

Abstract: A reputability analysis system receives a domain assessment request associated with a domain and accesses a database to find a match for the domain. A reputability score is derived according to a hierarchical analysis of a matching domain in the database. Traceability, accountability, and association information associated with the domain assessment request may also be used to adjust the reputability score.

Abstract: Described in an example embodiment herein is a method for extracting values from a plurality of data fields from a log file using a grammar file. The plurality of data fields and a procedure for extracting values from the plurality of data fields are defined in the grammar file. Extracted values are analyzed and graphically represented.

Abstract: A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.

Abstract: A method and mechanism for managing access to a plurality of registers in a processing device are contemplated. A processing device includes multiple nodes coupled to a ring bus, each of which include one or more registers which may be accessed by processes executing within the device. Also coupled to the ring bus is a ring control unit which is configured to initiate transactions targeted to nodes on the ring bus. Each of the nodes are configured receive and process bus transaction with a fixed latency whether or not the first transaction is targeted to the receiving node. The ring control unit is configured to periodically convey idle transactions on the ring bus in order to allow nodes responding to indeterminate transactions to gain access to the bus.

Abstract: A data attribution system uses a unique identifier (UID) that uniquely identifies a particular individual. A search is conducted of different data sources and, different types of profile information associated with the UID is extracted from the data sources. The different types of profile information associated with the same UID is aggregated together and displayed in a same screen presentation on a user interface.

Abstract: A microprocessor capable of decoding a plurality of instructions associated with a plurality of threads is disclosed. The microprocessor may comprise a first array comprising a first plurality of microcode operations associated with an instruction from within the plurality, the first array capable of delivering a first predetermined number of microcode operations from the first plurality of microcode operations. The microprocessor may further comprise a second array comprising a second plurality of microcode operations, the second array capable of providing one or more of the second plurality of microcode operations in the event that the instruction decodes into more than the first predetermined number of microcode operations. The microprocessor may further comprise an arbiter coupled between the first and second arrays, where the arbiter may determine which thread from the plurality of threads accesses the second array.

Abstract: A method and apparatus for implementing out-of-order memory transactions in a multithreaded, multicore processor. In the present invention, circular queue comprising a plurality of queue buffers is used to store load data returned by a memory unit in response to a request issued by a processing module, such as a stream processing unit, in a processing core. As requests are issued, a destination queue buffer ID tag is transmitted as part of the request. When the request is returned, that destination number is reflected back and is used to control which queue within the circular queue will be used to store the retuned load data. Separate pointers are used to indicate the order of the queues to be read and the order of the queues to be written. The method and apparatus implemented by the present invention allows out-of-order data to be processed efficiently, thereby improving the performance of a fine grain multithreaded, multi-core processor.

Abstract: A method and apparatus for improved performance for reloading translation look-aside buffers in multithreading, multi-core processors. TSB prediction is accomplished by hashing a plurality of data parameters and generating an index that is provided as an input to a predictor array to predict the TSB page size. In one embodiment of the invention, the predictor array comprises two-bit saturating up-down counters that are used to enhance the accuracy of the TSB prediction. The saturating up-down counters are configured to avoid making rapid changes in the TSB prediction upon detection of an error. Multiple misses occur before the prediction output is changed. The page size specified by the predictor index is searched first. Using the technique described herein, errors are minimized because the counter leads to the correct result at least half the time.

Abstract: The present invention relates to novel compounds useful as dipeptidyl peptidase IV (DPP-IV) inhibitors of the formula: wherein X, Y, a, R1, and R2 are as defined herein.

Abstract: The present invention relates to novel compounds useful as dipeptidyl peptidase IV (DPP-IV) inhibitors of the formula: wherein X, Y, a, R1, and R2 are as defined herein.