Patents by Inventor Manish Umedlal Patel
Manish Umedlal Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9438212Abstract: A circuit generates low-skew true and complement output signals from an input signal using an inverter, true signal generation circuitry, and complement signal generation circuitry. The inverter operates between a high-voltage reference source (VDD) and a low-voltage reference source (VSS) and inverts the input signal to generate a delayed complement input signal. The true signal generation circuitry, which comprises a p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a true output signal. The complement signal generation circuitry, which also comprises p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a complement output signal.Type: GrantFiled: November 30, 2012Date of Patent: September 6, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Manish Trivedi, Manish Umedlal Patel
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Patent number: 9412424Abstract: A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation.Type: GrantFiled: December 16, 2013Date of Patent: August 9, 2016Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Ashish Kumar, Manish Umedlal Patel
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Patent number: 9275686Abstract: A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks.Type: GrantFiled: May 28, 2014Date of Patent: March 1, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Manish Umedlal Patel, Dharmendra Kumar Rai, Mohammed Rahim Chand Seikh
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Publication number: 20150348594Abstract: A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Applicant: LSI CORPORATIONInventors: Manish Umedlal Patel, Dharmendra Kumar Rai, Mohammed Rahim Chand Seikh
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Publication number: 20140286116Abstract: A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation.Type: ApplicationFiled: December 16, 2013Publication date: September 25, 2014Applicant: STMicroelectronics International N.V.Inventors: Ashish KUMAR, Manish Umedlal PATEL
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Patent number: 8830771Abstract: A memory device includes a memory array comprising a including of memory cells, and control circuitry coupled to the memory array. The control circuitry includes write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry includes a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch.Type: GrantFiled: May 17, 2012Date of Patent: September 9, 2014Assignee: LSI CorporationInventors: Shailendra Sharad, Manish Umedlal Patel, Diwakar Ramadasu, Setti Shanmukheswara Rao
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Publication number: 20140152366Abstract: A circuit generates low-skew true and complement output signals from an input signal using an inverter, true signal generation circuitry, and complement signal generation circuitry. The inverter operates between a high-voltage reference source (VDD) and a low-voltage reference source (VSS) and inverts the input signal to generate a delayed complement input signal. The true signal generation circuitry, which comprises a p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a true output signal. The complement signal generation circuitry, which also comprises p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a complement output signal.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Applicant: LSI CorporationInventors: Manish Trivedi, Manish Umedlal Patel
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Publication number: 20140152345Abstract: A latch circuit comprises true and complement data nodes. During a setup period of a latching operation, true node setup circuitry draws the true data node toward an input data signal in parallel with complement node setup circuitry drawing the complement node upward toward a high-voltage reference source (VDD) when the data signal is low or downward toward a low-voltage reference source (VSS) when the data signal is high. After the setup period, true and complement clock signals are used as control signals to turn the setup circuitry off and amplification circuitry on. The amplification circuitry, which comprises a pair of cross-coupled inverters coupled between VDD and VSS, is capable of resolving relatively small voltage differentials between the true and complement nodes by pulling the true node (i) upward toward VDD when the data signal is high and (ii) downward toward VSS when the data signal is low.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Applicant: LSI CorporationInventors: Manish Trivedi, Manish Umedlal Patel
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Patent number: 8625372Abstract: A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation.Type: GrantFiled: December 21, 2009Date of Patent: January 7, 2014Assignee: STMicroelectronics International N.V.Inventors: Ashish Kumar, Manish Umedlal Patel
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Publication number: 20130308398Abstract: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry comprises a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch.Type: ApplicationFiled: May 17, 2012Publication date: November 21, 2013Applicant: LSI CorporationInventors: Shailendra Sharad, Manish Umedlal Patel, Diwakar Ramadasu, Setti Shanmukheswara Rao
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Patent number: 8588024Abstract: A static memory system with multiple memory cell that, in response to a reset signal, simultaneously resets or clears a segment of the memory cells in the memory. Clearing the entire memory or a portion thereof is accomplished by sequencing though a subset of address bits while asserting the reset signal.Type: GrantFiled: March 9, 2011Date of Patent: November 19, 2013Assignee: LSI CorporationInventors: Manish Umedlal Patel, Vikash
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Publication number: 20130258794Abstract: A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to the memory array. The sensing circuitry comprises a plurality of output sense amplifiers configured to sense stored data associated with respective columns of the memory array, and sense amplifier control circuitry configured to generate a sense amplifier control signal for application to control inputs of respective ones of the output sense amplifiers. The sense amplifier control circuitry comprises reaction time tracking circuitry including at least one dummy sense amplifier configured to track reaction time of one or more of the output sense amplifiers, with the sense amplifier control signal being generated at least in part responsive to an output signal of the dummy sense amplifier.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Applicant: LSI CorporationInventors: Shailendra Sharad, Manish Umedlal Patel, Setti Shanmukheswara Rao
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Patent number: 8400856Abstract: A memory device includes a memory array including a plurality of memory cells, sensing circuitry coupled to at least a given bitline associated with a particular column of the memory cells of the memory array, and access time acceleration circuitry coupled to the bitline. The access time acceleration circuitry is configured to control an amount of time required by the sensing circuitry to access data stored in a given one of the memory cells in the particular column of memory cells, by providing in a current access cycle at least a selected one of a plurality of different supplemental charging and discharging paths for the bitline based at least in part on data accessed using the bitline in a previous access cycle.Type: GrantFiled: February 22, 2011Date of Patent: March 19, 2013Assignee: LSI CorporationInventor: Manish Umedlal Patel
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Publication number: 20120230143Abstract: Described embodiments provide a static memory system with multiple memory cell that, in response to a reset signal, simultaneously resets or clears a segment of the memory cells in the memory. Clearing the entire memory or a portion thereof is accomplished by sequencing though a subset of address bits while asserting the reset signal.Type: ApplicationFiled: March 9, 2011Publication date: September 13, 2012Inventors: Manish Umedlal Patel, Vikash
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Publication number: 20120213024Abstract: A memory device includes a memory array comprising a plurality of memory cells, sensing circuitry coupled to at least a given bitline associated with a particular column of the memory cells of the memory array, and access time acceleration circuitry coupled to the bitline. The access time acceleration circuitry is configured to control an amount of time required by the sensing circuitry to access data stored in a given one of the memory cells in the particular column of memory cells, by providing in a current access cycle at least a selected one of a plurality of different supplemental charging and discharging paths for the bitline based at least in part on data accessed using the bitline in a previous access cycle.Type: ApplicationFiled: February 22, 2011Publication date: August 23, 2012Inventor: Manish Umedlal Patel
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Publication number: 20100157708Abstract: A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation.Type: ApplicationFiled: December 21, 2009Publication date: June 24, 2010Applicant: STMICROELECTRONICS Pvt. Ltd.Inventors: Ashish Kumar, Manish Umedlal Patel