Patents by Inventor Manjunatha G. PRABHU

Manjunatha G. PRABHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11239087
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: February 1, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Heng Yang, David C. Pritchard, George J. Kluth, Anurag Mittal, Hongru Ren, Manjunatha G. Prabhu, Kai Sun, Neha Nayyar, Lixia Lei
  • Patent number: 10819110
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anil Kumar, Manjunatha G. Prabhu, Alain F. Loiseau, Mahbub Rashed, Sushama Davar
  • Publication number: 20200058515
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Heng YANG, David C. PRITCHARD, George J. KLUTH, Anurag MITTAL, Hongru REN, Manjunatha G. PRABHU, Kai SUN, Neha NAYYAR, Lixia LEI
  • Patent number: 10497576
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Heng Yang, David C. Pritchard, George J. Kluth, Anurag Mittal, Hongru Ren, Manjunatha G. Prabhu, Kai Sun, Neha Nayyar, Lixia Lei
  • Publication number: 20190267801
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.
    Type: Application
    Filed: February 27, 2018
    Publication date: August 29, 2019
    Inventors: Anil KUMAR, Manjunatha G. PRABHU, Alain F. LOISEAU, Mahbub RASHED, Sushama DAVAR