Patents by Inventor Manjusha Manchikalapudi

Manjusha Manchikalapudi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9401706
    Abstract: Techniques and mechanisms for switching between a plurality of inputs each to receive a respective analog signal to be transmitted. In an embodiment, switch circuitry comprises a first input to receive a first signal, a second input to receive a second signal, and one or more T-coil circuits including a first T-coil circuit. A first configuration of the switch circuitry includes a first signal path via a first switch coupled between the first input and a primary input node of the first T-coil circuit. A second configuration of the switch circuitry includes a second signal path via a second switch coupled between the second input and a secondary input node of the first T-coil circuit. In an embodiment, control logic transitions the switch circuitry among a plurality of configurations including the first configuration and the second configuration.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: July 26, 2016
    Assignee: Lattice Semiconductor Corporation
    Inventors: Prashanth Tirunagari, Vinayak Agrawal, Namrta Sharma, Manjusha Manchikalapudi, Rahul Velitheri
  • Patent number: 9240878
    Abstract: Techniques and methods for performing asymmetric, full-duplex communication via a signal line. In an embodiment, a transceiver includes transmit circuitry to transmit a first signal via a node coupled to a signal line, where the first signal is transmitted concurrently with the transceiver receiving a second signal via the node at a substantially different data rate than that of the first signal. In another embodiment, signal processing circuitry of the transceiver detects a composite signal at the node, the composite signal including a combination of the first signal and the second signal. Based on the combination of the first signal and the second signal, the signal processing circuitry generates a processed signal, including the signal processing circuitry reducing a contribution by the first signal. The processed signal is provided to receiver circuitry of the transceiver.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: January 19, 2016
    Assignee: Lattice Semiconductor Corporation
    Inventors: Rahul Velitheri, Vinayak Agrawal, Namrta Sharma, Prashanth Tirunagari, Manjusha Manchikalapudi
  • Publication number: 20150215105
    Abstract: Techniques and methods for performing asymmetric, full-duplex communication via a signal line. In an embodiment, a transceiver includes transmit circuitry to transmit a first signal via a node coupled to a signal line, where the first signal is transmitted concurrently with the transceiver receiving a second signal via the node at a substantially different data rate than that of the first signal. In another embodiment, signal processing circuitry of the transceiver detects a composite signal at the node, the composite signal including a combination of the first signal and the second signal. Based on the combination of the first signal and the second signal, the signal processing circuitry generates a processed signal, including the signal processing circuitry reducing a contribution by the first signal. The processed signal is provided to receiver circuitry of the transceiver.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 30, 2015
    Applicant: Silicon Image, Inc.
    Inventors: Rahul Velitheri, Vinayak Agrawal, Namrta Sharma, Prashanth Tirunagari, Manjusha Manchikalapudi
  • Publication number: 20150214943
    Abstract: Techniques and mechanisms for switching between a plurality of inputs each to receive a respective analog signal to be transmitted. In an embodiment, switch circuitry comprises a first input to receive a first signal, a second input to receive a second signal, and one or more T-coil circuits including a first T-coil circuit. A first configuration of the switch circuitry includes a first signal path via a first switch coupled between the first input and a primary input node of the first T-coil circuit. A second configuration of the switch circuitry includes a second signal path via a second switch coupled between the second input and a secondary input node of the first T-coil circuit. In an embodiment, control logic transitions the switch circuitry among a plurality of configurations including the first configuration and the second configuration.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 30, 2015
    Applicant: Silicon Image, Inc.
    Inventors: Prashanth Tirunagari, Vinayak Agrawal, Namrta Sharma, Manjusha Manchikalapudi, Rahul Velitheri