Patents by Inventor Mankyu Yang
Mankyu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136400Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.Type: ApplicationFiled: January 5, 2024Publication date: April 25, 2024Inventors: Alexander Derrickson, Vibhor Jain, Judson R. Holt, Jagar Singh, Mankyu Yang
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Patent number: 11935923Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.Type: GrantFiled: November 12, 2021Date of Patent: March 19, 2024Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Alexander Derrickson, Vibhor Jain, Judson R. Holt, Jagar Singh, Mankyu Yang
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Patent number: 11804542Abstract: The present disclosure relates to semiconductor structures and, more particularly, to annular bipolar transistors and methods of manufacture. The structure includes: a substate material; a collector region parallel to and above the substrate material; an intrinsic base region surrounding the collector region; an emitter region above the intrinsic base region; and an extrinsic base region contacting the intrinsic base region.Type: GrantFiled: December 21, 2021Date of Patent: October 31, 2023Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Alexander M. Derrickson, Arkadiusz Malinowski, Jagar Singh, Mankyu Yang, Judson R. Holt
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Patent number: 11652142Abstract: A structure for a lateral bipolar junction transistor is provided. The structure comprising an emitter including a first concentration of a first dopant. A collector including a second concentration of the first dopant, the first concentration of the first dopant may be different from the second concentration of the first dopant. An intrinsic base may be laterally arranged between the emitter and the collector, and an extrinsic base region may be above the intrinsic base. An emitter extension may be arranged adjacent to the emitter, whereby the emitter extension laterally extends under a portion of the extrinsic base region. A halo region may be arranged adjacent to the emitter extension, whereby the halo region laterally extends under another portion of the extrinsic base region.Type: GrantFiled: September 22, 2021Date of Patent: May 16, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Mankyu Yang, Richard Taylor, III, Alexander Derrickson, Alexander Martin, Jagar Singh, Judson Robert Holt, Haiting Wang
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Publication number: 20230092435Abstract: A structure for a lateral bipolar junction transistor is provided. The structure comprising an emitter including a first concentration of a first dopant. A collector including a second concentration of the first dopant, the first concentration of the first dopant may be different from the second concentration of the first dopant. An intrinsic base may be laterally arranged between the emitter and the collector, and an extrinsic base region may be above the intrinsic base. An emitter extension may be arranged adjacent to the emitter, whereby the emitter extension laterally extends under a portion of the extrinsic base region. A halo region may be arranged adjacent to the emitter extension, whereby the halo region laterally extends under another portion of the extrinsic base region.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Inventors: MANKYU YANG, RICHARD TAYLOR, III, ALEXANDER DERRICKSON, ALEXANDER MARTIN, JAGAR SINGH, JUDSON ROBERT HOLT, HAITING WANG
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Publication number: 20230067486Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.Type: ApplicationFiled: November 12, 2021Publication date: March 2, 2023Inventors: Alexander Derrickson, Vibhor Jain, Judson R. Holt, Jagar Singh, Mankyu Yang
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Publication number: 20230063301Abstract: The present disclosure relates to semiconductor structures and, more particularly, to annular bipolar transistors and methods of manufacture.Type: ApplicationFiled: December 21, 2021Publication date: March 2, 2023Inventors: Alexander M. Derrickson, Arkadiusz Malinowski, Jagar Singh, Mankyu Yang, Judson R. Holt
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Patent number: 11588044Abstract: Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.Type: GrantFiled: December 2, 2020Date of Patent: February 21, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Alexander M. Derrickson, Mankyu Yang, Richard F. Taylor, III, Jagar Singh, Alexander L. Martin
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Patent number: 11575029Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.Type: GrantFiled: May 19, 2021Date of Patent: February 7, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Alexander M. Derrickson, Richard F. Taylor, III, Mankyu Yang, Alexander L. Martin, Judson R. Holt, Jagar Singh
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Publication number: 20230032080Abstract: Disclosed is a semiconductor structure that includes an asymmetric lateral bipolar junction transistor (BJT). The BJT includes an emitter, a base, a collector extension and a collector arranged side-by-side (i.e., laterally) across a semiconductor layer. The emitter, collector and collector extension have a first type conductivity with the collector extension having a lower conductivity level than either the emitter or the collector. The base has a second type conductivity that is different from the first type conductivity. With such a lateral configuration, the BJT can be easily integrated with CMOS devices on advanced SOI technology platforms. With such an asymmetric configuration and, particularly, given the inclusion of the collector extension but not an emitter extension, the BJT can achieve a relatively high collector-emitter breakdown voltage (Vbr-CEO) without a significant risk of leakage currents at high voltages. Also disclosed are method embodiments for forming such a semiconductor structure.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Applicant: GLOBALFOUNDRIES U.S. Inc.Inventors: Alexander M. Derrickson, Mankyu Yang, Judson R. Holt, Jagar Singh, Alexander L. Martin, Richard F. Taylor, III
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Publication number: 20220376093Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.Type: ApplicationFiled: May 19, 2021Publication date: November 24, 2022Applicant: GLOBALFOUNDRIES U.S. Inc.Inventors: Alexander M. Derrickson, Richard F. Taylor, III, Mankyu Yang, Alexander L. Martin, Judson R. Holt, Jagar Singh
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Publication number: 20220173230Abstract: Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.Type: ApplicationFiled: December 2, 2020Publication date: June 2, 2022Inventors: Alexander M. Derrickson, Mankyu Yang, Richard F. Taylor, III, Jagar Singh, Alexander L. Martin
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Patent number: 11276770Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate controlled transistors and methods of manufacture. The structure includes: an emitter region; a collector region; base regions on opposing sides of the emitter region and the collector region; and a gate structure composed of a body region and leg regions, the body region being located between the base regions on opposing sides of the emitter region and the collector region, and the leg regions isolating the base regions from both the emitter region and the collector region.Type: GrantFiled: November 5, 2019Date of Patent: March 15, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Mankyu Yang, Jagar Singh, Alexander Martin, John J. Ellis-Monaghan
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Publication number: 20210134987Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate controlled transistors and methods of manufacture. The structure includes: an emitter region; a collector region; base regions on opposing sides of the emitter region and the collector region; and a gate structure composed of a body region and leg regions, the body region being located between the base regions on opposing sides of the emitter region and the collector region, and the leg regions isolating the base regions from both the emitter region and the collector region.Type: ApplicationFiled: November 5, 2019Publication date: May 6, 2021Inventors: Mankyu YANG, Jagar SINGH, Alexander MARTIN, John J. ELLIS-MONAGHAN
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Patent number: 10796973Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.Type: GrantFiled: May 29, 2019Date of Patent: October 6, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta
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Patent number: 10790204Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.Type: GrantFiled: November 9, 2018Date of Patent: September 29, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta
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Publication number: 20200152530Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.Type: ApplicationFiled: November 9, 2018Publication date: May 14, 2020Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta
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Publication number: 20200152531Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.Type: ApplicationFiled: May 29, 2019Publication date: May 14, 2020Inventors: Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward Maciejewski, Brian Greene, Atsushi Ogino, Vikrant Chauhan, Prianka Sengupta