Abstract: A method and system for allocating data streams that includes receiving, at an allocator, a data stream. The data stream includes a memory address and data associated with the memory address. The method also includes examining, by the allocator, the data stream to make a determination that the data stream is a soft allocating data stream, and then sending, from the allocator based on the determination, a plurality of write probes to a plurality of caches, wherein each write probe of the plurality of write probes includes at least part of the memory address. Additionally, the method includes receiving, at the allocator in response to a write probe of the plurality of write probes, a cache line present acknowledgement from a cache of the plurality of caches, and directing, by the allocator in response to the cache line present acknowledgement, the data of the data stream to the cache.

Abstract: A method and system for dynamic flow control using credit sharing that includes allocating portions of credits to senders, wherein each of the credits is for communicating with a receiver; transmitting, by a first sender of the senders, a first message to the receiver using a first credit of a first portion of the credits; decrementing, in response to transmitting the first message, a credit balance of the first sender by one; and determining that the credit balance of the first sender is zero. The method also includes sending to a second sender of the senders, by the first sender, in response to the credit balance being zero, a first request for a second credit; receiving from the second sender, in response to the first request, a first response comprising the second credit; and transmitting, by the first sender, a second message to the receiver using the second credit.

Abstract: A method and system for dynamic flow control using credit sharing that includes allocating portions of credits to senders, wherein each of the credits is for communicating with a receiver; transmitting, by a first sender of the senders, a first message to the receiver using a first credit of a first portion of the credits; decrementing, in response to transmitting the first message, a credit balance of the first sender by one; and determining that the credit balance of the first sender is zero. The method also includes sending to a second sender of the senders, by the first sender, in response to the credit balance being zero, a first request for a second credit; receiving from the second sender, in response to the first request, a first response comprising the second credit; and transmitting, by the first sender, a second message to the receiver using the second credit.

Abstract: A method and system for allocating data streams that includes receiving, at an allocator, a data stream. The data stream includes a memory address and data associated with the memory address. The method also includes examining, by the allocator, the data stream to make a determination that the data stream is a soft allocating data stream, and then sending, from the allocator based on the determination, a plurality of write probes to a plurality of caches, wherein each write probe of the plurality of write probes includes at least part of the memory address. Additionally, the method includes receiving, at the allocator in response to a write probe of the plurality of write probes, a cache line present acknowledgement from a cache of the plurality of caches, and directing, by the allocator in response to the cache line present acknowledgement, the data of the data stream to the cache.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for communicating between domains of a computing system, where at least one of the domains operates on a skipped clock signal. Communication from a skipped clock domain to a non-skipped clock domain, or free running domain, may include a valid signal component configured to indicate when a new data packet is available and one or more counters associated with the domains to count received data packets for acknowledgement or credit purposes. The free running domain may receive data packets from any number of skipped clock domains through the communication scheme described herein. Communication from a free running domain to a skipped clock domain may include delaying transmitted data packets to correspond with the cycles of the skipped clock signal to ensure that transmitted data packets arrive at the skipped clock domain to be properly read on a skipped clock cycle.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for communicating between domains of a computing system, where at least one of the domains operates on a skipped clock signal. Communication from a skipped clock domain to a non-skipped clock domain, or free running domain, may include a valid signal component configured to indicate when a new data packet is available and one or more counters associated with the domains to count received data packets for acknowledgement or credit purposes. The free running domain may receive data packets from any number of skipped clock domains through the communication scheme described herein. Communication from a free running domain to a skipped clock domain may include delaying transmitted data packets to correspond with the cycles of the skipped clock signal to ensure that transmitted data packets arrive at the skipped clock domain to be properly read on a skipped clock cycle.