Patents by Inventor Manoj Bist

Manoj Bist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for merging EDA coverage logs of coverage data
    Patent number: 8904319
    Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 2, 2014
    Assignee: Synopsys, Inc.
    Inventors: Manoj Bist, Sandeep Mehrotra
  • Method and apparatus for merging EDA coverage logs of coverage data
    Patent number: 8219947
    Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: July 10, 2012
    Assignee: Synopsys, Inc.
    Inventors: Manoj Bist, Sandeep Mehrotra
  • Method and Apparatus for Merging EDA Coverage Logs of Coverage Data
    Publication number: 20110283246
    Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.
    Type: Application
    Filed: July 22, 2011
    Publication date: November 17, 2011
    Applicant: Synopsys, Inc.
    Inventors: Manoj Bist, Sandeep Mehrotra
  • Method and apparatus for merging EDA coverage logs of coverage data
    Patent number: 8001505
    Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: August 16, 2011
    Assignee: Synopsys, Inc.
    Inventors: Manoj Bist, Sandeep Mehrotra
  • Method and Apparatus for Merging EDA Coverage Logs of Coverage Data
    Publication number: 20100070940
    Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.
    Type: Application
    Filed: September 15, 2008
    Publication date: March 18, 2010
    Applicant: Synopsys, Inc.
    Inventors: Manoj Bist, Sandeep Mehrotra
  • Method and Apparatus for Merging EDA Coverage Logs of Coverage Data
    Publication number: 20100070935
    Abstract: An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.
    Type: Application
    Filed: September 15, 2008
    Publication date: March 18, 2010
    Applicant: SYNOPSYS, INC.
    Inventors: Manoj Bist, Sandeep Mehrotra