Patents by Inventor Manoj Dusanapudi

Manoj Dusanapudi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9424159
    Abstract: Performance measurement of hardware accelerators, where one or more computer processors are operably coupled to at least one hardware accelerator, and a computer memory is operatively coupled to the one or more computer processors, including operating by the one or more processors the accelerator at saturation, submitting data processing tasks by the processors to the accelerator at a rate that saturates the data processing resources of the accelerator, causing the accelerator to decline at least some of the submitted tasks; and while the accelerator is operating at saturation, measuring by the processors accelerator performance according to a period of time during which the accelerator accepts a plurality of submitted tasks.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: August 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Sairam Kamaraju, Anil Krishna
  • Patent number: 9298516
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for verifying transitions between logical partition configurations. A computer system divides the physical resources of a processing core into logical partitions, each of which has at least one processing subcore. The computer system loads the contexts of the logical partitions and assigns test cases to each processing subcore. The processing subcore executes the test case, verifying the context of the logical partition. The computer system reassigns the test cases to different processing cores in anticipation of reconfiguring the number of logical partitions on the processing core. The computing system reconfigures the number of logical partitions on the processing core and executes the test cases as assigned on the reconfigured logical partitions.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Manoj Dusanapudi, Varun Mallikarjunan
  • Patent number: 9286133
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for verifying transitions between logical partition configurations. A computer system divides the physical resources of a processing core into logical partitions, each of which has at least one processing subcore. The computer system loads the contexts of the logical partitions and assigns test cases to each processing subcore. The processing subcore executes the test case, verifying the context of the logical partition. The computer system reassigns the test cases to different processing cores in anticipation of reconfiguring the number of logical partitions on the processing core. The computing system reconfigures the number of logical partitions on the processing core and executes the test cases as assigned on the reconfigured logical partitions.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Manoj Dusanapudi, Varun Mallikarjunan
  • Patent number: 9287005
    Abstract: Using an “optimized” test case for testing hardware and/or software of a computer. The optimized test case is designed to be run on a data storage device including multiple read locations and multiple write locations. Initialization data is written, on the data storage device, only to the write locations of the data storage device. The optimized test case is run on the data storage device in a manner so that the optimized test case will only write data to each write location after that write location has had initialization data written to that write location. The optimized test case defines read locations and write locations so that, during running of the optimized test case, all read locations which are also write locations will be written by a write instruction of the test case before being read by a read instruction of the test case.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Bhavesh D. Budhabhatti, Manoj Dusanapudi, Sairam Kamaraju, Varun Mallikarjunan, Subrat K. Panda
  • Patent number: 9128887
    Abstract: Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: September 8, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi, Girisankar Paulraj, Saravanan Sethuraman, Diyanesh B. Vidyapoornachary
  • Publication number: 20150170764
    Abstract: Using an “optimized” test case for testing hardware and/or software of a computer. The optimized test case is designed to be run on a data storage device including multiple read locations and multiple write locations. Initialization data is written, on the data storage device, only to the write locations of the data storage device. The optimized test case is run on the data storage device in a manner so that the optimized test case will only write data to each write location after that write location has had initialization data written to that write location. The optimized test case defines read locations and write locations so that, during running of the optimized test case, all read locations which are also write locations will be written by a write instruction of the test case before being read by a read instruction of the test case.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: International Business Machines Corporation
    Inventors: Bhavesh D. Budhabhatti, Manoj Dusanapudi, Sairam Kamaraju, Varun Mallikarjunan, Subrat K. Panda
  • Patent number: 9043569
    Abstract: A method and computer-readable storage media are provided for rearranging data in physical memory units. In one embodiment, a method may include monitoring utilization counters. The method may further include, comparing the utilization counters for a match with an instance in a first table containing one or more instances when data may be rearranged in the physical memory units. The table may further include where the data should be relocated by a rearrangement. The method may also include, continuing to monitor the utilization counters if a match is not found with an instance in the first table. The method may further include, rearranging the data in the physical memory units if a match between the utilization counters and an instance in the first table is found.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Dell, Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi
  • Patent number: 9015522
    Abstract: A method, system and computer program product are provided for implementing dynamic random access memory (DRAM) failure scenarios mitigation using buffer techniques delaying usage of RAS features in computer systems. A buffer is provided with a memory controller. Physical address data read/write failures are analyzed. Responsive to identifying predefined failure types for physical address data read/write failures, the buffer is used to selectively store and retrieve data.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Dell, Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi
  • Publication number: 20150106816
    Abstract: Performance measurement of hardware accelerators, where one or more computer processors are operably coupled to at least one hardware accelerator, and a computer memory is operatively coupled to the one or more computer processors, including operating by the one or more processors the accelerator at saturation, submitting data processing tasks by the processors to the accelerator at a rate that saturates the data processing resources of the accelerator, causing the accelerator to decline at least some of the submitted tasks; and while the accelerator is operating at saturation, measuring by the processors accelerator performance according to a period of time during which the accelerator accepts a plurality of submitted tasks.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 16, 2015
    Applicant: International Business Machines Corporation
    Inventors: MANOJ DUSANAPUDI, SAIRAM KAMARAJU, ANIL KRISHNA
  • Publication number: 20150095607
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for verifying transitions between logical partition configurations. A computer system divides the physical resources of a processing core into logical partitions, each of which has at least one processing subcore. The computer system loads the contexts of the logical partitions and assigns test cases to each processing subcore. The processing subcore executes the test case, verifying the context of the logical partition. The computer system reassigns the test cases to different processing cores in anticipation of reconfiguring the number of logical partitions on the processing core. The computing system reconfigures the number of logical partitions on the processing core and executes the test cases as assigned on the reconfigured logical partitions.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Varun Mallikarjunan
  • Publication number: 20150095608
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for verifying transitions between logical partition configurations. A computer system divides the physical resources of a processing core into logical partitions, each of which has at least one processing subcore. The computer system loads the contexts of the logical partitions and assigns test cases to each processing subcore. The processing subcore executes the test case, verifying the context of the logical partition. The computer system reassigns the test cases to different processing cores in anticipation of reconfiguring the number of logical partitions on the processing core. The computing system reconfigures the number of logical partitions on the processing core and executes the test cases as assigned on the reconfigured logical partitions.
    Type: Application
    Filed: December 5, 2013
    Publication date: April 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Varun Mallikarjunan
  • Publication number: 20140359241
    Abstract: A method and computer-readable storage media are provided for rearranging data in physical memory units. In one embodiment, a method may include monitoring utilization counters. The method may further include, comparing the utilization counters for a match with an instance in a first table containing one or more instances when data may be rearranged in the physical memory units. The table may further include where the data should be relocated by a rearrangement. The method may also include, continuing to monitor the utilization counters if a match is not found with an instance in the first table. The method may further include, rearranging the data in the physical memory units if a match between the utilization counters and an instance in the first table is found.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Timothy J. Dell, Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi
  • Patent number: 8832502
    Abstract: A method includes executing a first post-silicon testing program by a reference model. During the execution of the first post-silicon testing program, one or more test-cases are generated. The first post-silicon testing program is executed in an offline generation mode. During execution of the first post-silicon testing program each test case is generated in a different memory location. After the execution, generating a second post-silicon testing program that is configured to execute the one or more test-cases. The method further includes executing the second post-silicon testing program on an acceleration platform.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Wisam Kadry, Shakti Kapoor, Dimtry Krestyashyn, Shimon Landa, Amir Nahir, John Schumann, Gil Eliezer Shurek, Vitali Sokhin
  • Publication number: 20140236561
    Abstract: A method of testing cache coherency in a computer system design allocates different portions of a single cache line for use by accelerators and processors. The different portions of the cache line can have different sizes, and the processors and accelerators can operate in the simulation at different frequencies. The verification system can control execution of the instructions to invoke different modes of the coherency mechanism such as direct memory access or cache intervention. The invention provides a further opportunity to test any accelerator having an original function and an inverse function by allocating cache lines to generate an original function output, allocating cache lines to generate an inverse function output based on the original function output, and verifying correctness of the original and inverse functions by comparing the inverse function output to the original function input.
    Type: Application
    Filed: September 26, 2013
    Publication date: August 21, 2014
    Applicant: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Sairam Kamaraju, Shakti Kapoor
  • Publication number: 20140237194
    Abstract: A method of testing cache coherency in a computer system design allocates different portions of a single cache line for use by accelerators and processors. The different portions of the cache line can have different sizes, and the processors and accelerators can operate in the simulation at different frequencies. The verification system can control execution of the instructions to invoke different modes of the coherency mechanism such as direct memory access or cache intervention. The invention provides a further opportunity to test any accelerator having an original function and an inverse function by allocating cache lines to generate an original function output, allocating cache lines to generate an inverse function output based on the original function output, and verifying correctness of the original and inverse functions by comparing the inverse function output to the original function input.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 21, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Manoj Dusanapudi, Sairam Kamaraju, Shakti Kapoor
  • Publication number: 20140157044
    Abstract: A method, system and computer program product are provided for implementing dynamic random access memory (DRAM) failure scenarios mitigation using buffer techniques delaying usage of RAS features in computer systems. A buffer is provided with a memory controller. Physical address data read/write failures are analyzed. Responsive to identifying predefined failure types for physical address data read/write failures, the buffer is used to selectively store and retrieve data.
    Type: Application
    Filed: December 4, 2012
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy J. Dell, Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi
  • Publication number: 20140053016
    Abstract: Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi, Girisankar Paulraj, Saravanan Sethuraman, Diyanesh B. Vidyapoornachary
  • Publication number: 20140032966
    Abstract: A method, apparatus and product for hardware verification using acceleration platform. The method comprising executing a first post-silicon testing program by a reference model, wherein during said executing the first post-silicon testing program one or more test-cases are generated; generating a second post-silicon testing program that is configured to execute the one or more test-cases; and executing the second post-silicon testing program on an acceleration platform.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Wisam Kadry, Shakti Kapoor, Dimtry Krestyashyn, Shimon Landa, Amir Nahir, John Schumann, Gil (Eliezer) Shurek, Vitali Sokhin
  • Patent number: 8127192
    Abstract: During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store instruction after the lwarx instruction using the pseudo-random address. The store instruction is adapted to store the pseudo-random address in a predetermined memory location. The test pattern generator also builds an interrupt service routine that services an interrupt associated with the interrupt request; checks the predetermined memory location; determines that the pseudo-random address is located in the predetermined memory location; and executes a subsequent lwarx instruction using the pseudo-random address.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sampan Arora, Divya S. Anvekar, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Bhavani Shringari Nanjundiah
  • Patent number: 8099559
    Abstract: A system and method for intentionally invaliding translation entry valid bits in order to provoke storage interrupts when executing a test case is presented. Prior to executing the test case, an interrupt handler pseudo-randomly invalidates a number of translation entries included in a translation lookaside buffer (TLB) by changing particular valid bits in order to provoke initial storage interrupts, such as an instruction storage interrupt (ISI) or a data storage interrupt (DSI). Once the processor executes the test case that, in turn, triggers a storage interrupt, the interrupt handler uses an index counter to validate particular valid bits and invalidate other valid bits, thus provoking subsequent storage interrupts. In one embodiment, the interrupt handler also changes valid bits in a page table when the processor executes in a mode that accesses the page table in addition to the TLB.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Shubhodeep Roy Choudhury, Manoj Dusanapudi, Sunil Suresh Hatti, Shakti Kapoor, Rahul Sharad Moharil