Patents by Inventor Manoj K. Arora
Manoj K. Arora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9940238Abstract: A chip multiprocessor may include a first cluster and a second cluster, each having multiple cores of a processor, multiple co-located cache slices, and a memory controller. The processor stores directory information in a memory to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space to a second address space of the second cluster, the processor provides a quiesce period during which to block new read or write requests to the first cluster and the second cluster; drain read or write requests issued on the first cluster and the second cluster; and remove the block on new read or write requests. The processor may also update the directory information to change the cluster cache ownership of the first address space to the second address space of the second cluster.Type: GrantFiled: May 23, 2017Date of Patent: April 10, 2018Assignee: Intel CorporationInventors: Rahul Pal, Ishwar Agarwal, Manoj K. Arora
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Publication number: 20170255553Abstract: A chip multiprocessor may include a first cluster and a second cluster, each having multiple cores of a processor, multiple co-located cache slices, and a memory controller. The processor stores directory information in a memory to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space to a second address space of the second cluster, the processor provides a quiesce period during which to block new read or write requests to the first cluster and the second cluster; drain read or write requests issued on the first cluster and the second cluster; and remove the block on new read or write requests. The processor may also update the directory information to change the cluster cache ownership of the first address space to the second address space of the second cluster.Type: ApplicationFiled: May 23, 2017Publication date: September 7, 2017Inventors: Rahul Pal, Ishwar Agarwal, Manoj K. Arora
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Patent number: 9690706Abstract: Resolving coherency issues inherent in sharing distributed cache is described. A chip multiprocessor may include at least first and second processing clusters, each having multiple cores of a processor, multiple cache slices co-located with the multiple cores, and a memory controller (MC). The processor stores directory information in a memory coupled to the processor to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space, the processor may remap first lines of first cache slices, corresponding to the first address space, to second lines in second cache slices of the second cluster, and update the directory information (e.g., a state of the first cache lines) to change the cluster cache ownership of the first address space to the second cluster. One of the MCs may manage such updating of the directory.Type: GrantFiled: March 25, 2015Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Rahul Pal, Ishwar Agarwal, Manoj K. Arora
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Patent number: 9298629Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.Type: GrantFiled: November 21, 2014Date of Patent: March 29, 2016Assignee: Intel CorporationInventors: Sailesh Kottapalli, Henk G. Neefs, Rahul Pal, Manoj K. Arora, Dheemanth Nagaraj
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Patent number: 9235520Abstract: Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions. Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.Type: GrantFiled: December 20, 2011Date of Patent: January 12, 2016Assignee: Intel CorporationInventors: Manoj K. Arora, Robert G. Blankenship, Rahul Pal, Dheemanth Nagaraj
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Patent number: 9170946Abstract: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.Type: GrantFiled: December 21, 2012Date of Patent: October 27, 2015Assignee: Intel CorporationInventors: Herbert H. Hum, James R. Vash, Eric A. Gouldey, Ganesh Kumar, David Bubien, Manoj K. Arora, Luke Chang, Lavanya Nama, Mahak Gupta
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Publication number: 20150081977Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.Type: ApplicationFiled: November 21, 2014Publication date: March 19, 2015Inventors: SAILESH KOTTAPALLI, HENK G. NEEFS, RAHUL PAL, MANOJ K. ARORA, DHEEMANTH NAGARAJ
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Patent number: 8918592Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.Type: GrantFiled: December 27, 2013Date of Patent: December 23, 2014Assignee: Intel CorporationInventors: Sailesh Kottapalli, Henk G. Neefs, Rahul Pal, Manoj K. Arora, Dheemanth Nagaraj
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Publication number: 20140359230Abstract: Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions. Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.Type: ApplicationFiled: December 20, 2011Publication date: December 4, 2014Inventors: Manoj K. Arora, Robert G. Blankenship, Rahul Pal, Dheemanth Nagaraj
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Publication number: 20140181394Abstract: Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Inventors: Herbert H. Hum, James R. Vash, Eric A. Gouldey, Ganesh Kumar, David Bubien, Manoj K. Arora, Luke Chang, Lavanya Nama, Mahak Gupta
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Publication number: 20140115274Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.Type: ApplicationFiled: December 27, 2013Publication date: April 24, 2014Inventors: SAILESH KOTTAPALLI, HENK G. NEEFS, RAHUL PAL, MANOJ K. ARORA, DHEEMANTH NAGARAJ
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Patent number: 8656115Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.Type: GrantFiled: August 20, 2010Date of Patent: February 18, 2014Assignee: Intel CorporationInventors: Sailesh Kottapalli, Henk G. Neefs, Rahul Pal, Manoj K. Arora, Dheemanth Nagaraj
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Patent number: 8489822Abstract: In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.Type: GrantFiled: November 23, 2010Date of Patent: July 16, 2013Assignee: Intel CorporationInventors: Andrew Y. Sun, Henk G. Neefs, Rahul Pal, Manoj K. Arora, Ravindra P. Saraf
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Publication number: 20120131282Abstract: In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Inventors: Andrew Y. Sun, Henk G. Neefs, Rahul Pal, Manoj K. Arora, Ravindra P. Saraf
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Publication number: 20120047333Abstract: In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.Type: ApplicationFiled: August 20, 2010Publication date: February 23, 2012Inventors: SAILESH KOTTAPALLI, Henk G. Neefs, Rahul Pal, Manoj K. Arora, Dheemanth Nagaraj