Patents by Inventor Manoj Kumar Kumar Tiwari

Manoj Kumar Kumar Tiwari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Biasing cascode transistors of an output buffer circuit for operation over a wide range of supply voltages
    Patent number: 10454466
    Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 22, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Manoj Kumar Kumar Tiwari, Saiyid Mohammad Irshad Rizvi
  • BIASING CASCODE TRANSISTORS OF AN OUTPUT BUFFER CIRCUIT FOR OPERATION OVER A WIDE RANGE OF SUPPLY VOLTAGES
    Publication number: 20190312575
    Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.
    Type: Application
    Filed: January 22, 2019
    Publication date: October 10, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Manoj Kumar Kumar TIWARI, Saiyid Mohammad Irshad RIZVI
  • Biasing cascode transistor of an output buffer circuit for operation over a wide range of supply voltages
    Patent number: 10224922
    Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: March 5, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Manoj Kumar Kumar Tiwari, Saiyid Mohammad Irshad Rizvi