Abstract: Semiconductor packages that contain multiple stacked chips that are embedded in a pre-molded carrier frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. The land pad array contains inner terminals that are formed by first stud bumps that are located on a lower die. The land pad array also contains middle terminals that are formed by first conductive vias in a first molding layer embedding the first die. The first conductive vias are connected to second stud bumps that are located on a second die that is embedded in a second molding layer. The second molding layer contains second conductive vias that are connected to a carrier frame, the bottom of which forms the outer terminals of the land pad array.

Abstract: Semiconductor packages that contain multiple stacked chips that are embedded in a pre-molded carrier frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. The land pad array contains inner terminals that are formed by first stud bumps that are located on a lower die. The land pad array also contains middle terminals that are formed by first conductive vias in a first molding layer embedding the first die. The first conductive vias are connected to second stud bumps that are located on a second die that is embedded in a second molding layer. The second molding layer contains second conductive vias that are connected to a carrier frame, the bottom of which forms the outer terminals of the land pad array.

Abstract: A multichip discrete package with a leadframe having a plurality of leads and a first die attach pad (DAP), the first DAP having side portions that extend above the first DAP, a first discrete die bonded to the first DAP, at least a first wirebond which forms an electrical connections between the first discrete die and a first selected one of the plurality of leads, a metal plate attached to tops of the side portions forming a second DAP, a second discrete die bonded to the second DAP, at least a second wirebond which forms an electrical connections between the second discrete die and a second selected one of the leads; and encapsulating material formed around the first and second die and the first and second DAPs.

Abstract: Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a leadframe having an array of holes with a layout corresponding to the land pad array of the package, wherein the holes contain a thermally-conductive dielectric material with a via therein containing an electrically conductive material. The electrically conductive materials can extend past the bottom of the leadframe to form the land pad array of the packages. With such a configuration, the leadframe can act as an embedded heat sink in the package and there is no need to mount an additional heat sink to the package for thermal dissipation, allowing a thinner package to be manufactured. With such a configuration, the semiconductor packages have a full land pad array, providing a smaller footprint and a higher I/O capacity. Other embodiments are also described.

Abstract: A multichip discrete package with a leadframe having a plurality of leads and a first die attach pad (DAP), the first DAP having side portions that extend above the first DAP, a first discrete die bonded to the first DAP, at least a first wirebond which forms an electrical connections between the first discrete die and a first selected one of the plurality of leads, a metal plate attached to tops of the side portions forming a second DAP, a second discrete die bonded to the second DAP, at least a second wirebond which forms an electrical connections between the second discrete die and a second selected one of the leads; and encapsulating material formed around the first and second die and the first and second DAPs.

Abstract: Semiconductor packages that contain stacked chips on a micro-layered lead frame and methods for making such semiconductor packages are described. The semiconductor packages contain a full array of land pads that has been formed from a lead frame. The packages comprise multiple chips that are stacked vertically and separated by routing leads which are connected to the land pad array. The routing leads can be etched from a metal cladding layer that is provided between each set of stacked chips. Each chip and its routing leads can be encapsulated before the next chip is provided in the package. The semiconductor packages therefore have a high input/output capability with a small package footprint, a flexible routing capability, and a small thickness for multiple chips that are stacked in the package. Other embodiments are also described.