Patents by Inventor Manu Rehani

Manu Rehani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6807655
    Abstract: A method for adaptively providing parametric limits to identify defective die quantizes the die into a plurality of groups according to statistical distributions, such as intrinsic speed in one embodiment. For each quantization level, an intrinsic distribution of the parameter is derived. Adaptive screening limits are then set as a function of the intrinsic distribution. Dies are then screened according to their parametric values with respect to the adaptive limits.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: October 19, 2004
    Assignee: LSI Logic Corporation
    Inventors: Manu Rehani, Kevin Cota, David Abercrombie, Robert Madge
  • Patent number: 6658361
    Abstract: A method for determining an effective fatal defect count based on defects in a plurality of inspected integrated circuits includes acquiring defect information related to defects in the integrated circuits, and assigning defect weight values to each of the defects based on the defect information. The defect weight values are in N number of defect weight value ranges, including a lowest and a highest defect weight value range. For each integrated circuit, a heaviest defect is determined, where the heaviest defect is the defect on each integrated circuit having a highest defect weight value. For each of the N number of defect weight value ranges, a total number T(n) of the heaviest defects having a defect weight value within a defect weight value range n is determined, where n equals one to N.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: December 2, 2003
    Assignee: LSI Logic Corporation
    Inventors: Manu Rehani, Ramkumar Vaidyanathan, David A. Abercrombie
  • Patent number: 6512985
    Abstract: A computerized system for analyzing information associated with a process unit. A database contains historical information relating to previously compiled information. A secure input receives criteria from a restricted source. A computer mathematically determines a limit based upon the criteria. An open input receives the information associated with the process unit from multiple test locations. A compiler selectively adds to the database of historical information the information. The computer also selects at least a portion of the information based upon selection criteria. In addition, the computer manipulates the selected information based upon manipulation criteria. The manipulated information is compared against the limit. An output indicates a first disposition of the process unit when the manipulated information violates the limit. The output indicates a second disposition of the process unit when the manipulated information does not violate the limit.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: January 28, 2003
    Assignee: LSI Logic Corporation
    Inventors: Bruce J. Whitefield, Manu Rehani, John A. Knoch