Abstract: In certain aspects, a data storage device is provided including a distributed controller configured to communicate with a main controller; and first and second memory devices of respective first and second non-volatile memory technologies. The first and second memory devices are coupled to the distributed controller configured to control access to the first and second memory devices. In certain aspects, a system is provided including a main controller; first and second distributed controllers coupled to the main controller; at least one first memory device coupled to the first distributed controller; and at least one second memory device coupled to the second distributed controller. The main controller is configured to control access to the first and second distributed controllers. The first and second distributed controllers are configured to control access to the respective at least one first and second memory devices that include at least two non-volatile memory technologies.

Abstract: In certain aspects, a device may include a memory and a controller coupled to the memory. The controller may be configured to process data to form codewords and to send the codewords to the memory to be stored at locations of the memory. The controller may encode and tag the incoming data (from the host) to minimize the charge that is required to be stored in the non-volatile memory.

Abstract: In certain aspects, a device may include a memory and a controller coupled to the memory. The controller may be configured to process data to form codewords and to send the codewords to the memory to be stored at locations of the memory. The controller may encode and tag the incoming data (from the host) to minimize the charge that is required to be stored in the non-volatile memory.

Abstract: In certain aspects, devices, systems, and methods are provided for increasing endurance on a storage system having a plurality of components using adaptive code rates. A controller may be configured to receive a first data packet from a memory device; determine a bit error count for the first data packet; and determine whether the bit error count exceeds a predetermined threshold. When the bit error count exceeds the predetermined threshold, the controller corrects errors identified in the bit error count; generates and inserts pre-defined data into the first data packet at a location where errors occurred in the first data packet; and generates and inserts a tag into the first data packet. The tag includes information indicating a size and a location of the pre-defined data in the first data packet.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to process data to form codewords and to send the codewords to the memory to be stored at locations of the memory that are restricted based on a non-adjacency pattern.

Abstract: A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes sending an instruction to a host device to cause the host device to perform one or more specified computations. The method further includes receiving a response from the host device. The response is based on execution of the one or more specified computations.

Abstract: A method includes generating a first error correcting code (ECC) codeword and a second ECC codeword. The method further includes generating redundancy information based on at least a portion of the first ECC codeword and further based on at least a portion of the second ECC codeword. The method further includes storing the first ECC codeword, the second ECC codeword, and the redundancy information at a word line of a memory of a data storage device.

Abstract: A data storage device includes a memory that has a three-dimensional (3D) memory configuration, a controller, and a plurality of memory ports. The controller is configured to read mapping data from the memory. The mapping data maps the plurality of memory ports to the plurality of storage elements. The controller is further configured to, in response to receiving a command associated with a logical address, determine a physical address of the memory corresponding to the logical address, the physical address corresponding to a group of storage elements of the plurality of storage elements. The controller is further configured to select a memory port of the plurality of memory ports, where the memory port is mapped to the group of storage elements. The controller is further configured to access the group of storage elements via the memory port to perform first command.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to process data to form codewords and to send the codewords to the memory to be stored at locations of the memory that are restricted based on a non-adjacency pattern.

Abstract: A data storage device includes a nonvolatile memory and a controller having a decoder. The nonvolatile memory is operatively coupled to the controller. The nonvolatile memory is configured to store a set of bits. The decoder is configured to receive the set of bits from the memory. The decoder is further configured to perform a decoding operation using the set of bits based on a parity check matrix. The parity check matrix includes a block row. The block row has a first non-zero sub-matrix and a second non-zero sub-matrix that is separated from the first non-zero sub-matrix within the block row by at least a threshold number of null sub-matrices of the block row.

Abstract: A method includes generating a first error correcting code (ECC) codeword and a second ECC codeword. The method further includes generating redundancy information based on at least a portion of the first ECC codeword and further based on at least a portion of the second ECC codeword. The method further includes storing the first ECC codeword, the second ECC codeword, and the redundancy information at a word line of a memory of a data storage device.

Abstract: A method performed at a non-volatile memory of a data storage device includes determining, at error detection circuitry included in the non-volatile memory, an indication of a number of errors associated with a portion of the non-volatile memory. The method also includes providing the indication to a controller of the data storage device, where the controller includes error correction circuitry. The non-volatile memory has a 3D configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The non-volatile memory includes circuitry associated with operation of the memory cells.

Abstract: An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core.

Abstract: A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes receiving, at the controller, first data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, first dummy data, and second dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The first dummy data and the second dummy data prevent a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states.

Abstract: A data storage device includes a memory die. The memory die includes a memory having a three-dimensional (3D) memory configuration. A method includes sensing information stored at a region of the memory to generate sensed information. The method further includes adjusting one or more write parameters associated with the region in response to an error rate associated with the sensed information satisfying an error threshold.

Abstract: A method includes initiating a first decode operation of data at an error correction code (ECC) hard bit decoder in a data storage device that includes a controller and a memory. The method further includes, in response to the first decode operation indicating that the data is uncorrectable by the first decode operation, identifying one or more bits of the data that correspond to a disturb condition test pattern, changing a value of the one or more identified bits of the data to generate modified data, and initiating a second decode operation at the ECC hard bit decoder using the modified data.

Abstract: A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes receiving, at the controller, first data and second data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, the second data, and dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The dummy data prevents a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states.

Abstract: A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage. The controller is further configured to, at a second time, determine a second count of storage elements having threshold voltages within the voltage range. The controller is further configured to calculate an updated first reference voltage at least partially based on the first reference voltage, the first count, and the second count.

Abstract: A data storage device includes a memory including a group of storage elements. The memory is configured to read the group of the storage elements. A controller is coupled to the memory. The controller is configured to, in response to a first error correction code (ECC) procedure determining that a first plurality of bit values obtained using a first read voltage to read the group of storage elements is uncorrectable, instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values. The controller is further configured to compare the first plurality of bit values with the second plurality of bit values to identify a first set of bits having different values in the first plurality of bit values as compared to the second plurality of bit values and to change one or more values of the first plurality of bit values for one or more bits in the first set of bits to generate a first plurality of corrected bit values.

Abstract: A data storage device includes a non-volatile memory. The non-volatile memory may include a first word line, a second word line, and a third word line. The second word line may be between the first word line and the third word line. The non-volatile memory may further include a first string and a second string. The first string may be adjacent to the second string. The data storage device may further include circuitry configured to store parity information at a fourth word line of the non-volatile memory. The parity information may correspond to a combination of first data associated with the first word line and the first string, second data associated with the first word line and the second string, third data associated with the third word line and the first string, and fourth data associated with the third word line and the second string.