Abstract: An internal cooling system for an electric motor including a stator with stator laminations and stator slots, a motor winding including head windings and stator slot winding turns in the stator slots, the internal cooling system including an internal slot jacket configured to encapsulate the stator slot winding turns in the stator slots. The internal slot jacket and/or the internal slot jacket outside the plurality of ducts includes a plurality of ducts configured to conduct coolant in contact with the stator slot winding turns in the stator slots to extract winding losses. Each of the ducts includes a plurality of features to reduce thermal resistance.

Abstract: An internal cooling system for an electric motor comprising a Drive End, DE, casing and a Non-Drive End, NDE casing, a stator with stator laminations and stator slots, head windings and stator slot winding turns, the internal cooling system comprising a first liquid cooling channel and a second liquid cooling channel, a periphery casing liquid cooling jacket connected to the first liquid cooling channel and to the second liquid cooling channel, DE and a NDE casing liquid cooling jackets configured to be established inside the DE and NDE casings, respectively, and connected to the first liquid cooling channel and to the second liquid cooling channel, respectively, and a slot-through liquid cooling jacket connected to the NDE and a DE casing liquid cooling jackets and configured to be established through the stator slots and in contact with the head windings and the stator slot winding turns to extract winding losses.

Abstract: Systems, methods, and apparatus for complementary self-limiting logic are disclosed. In one or more embodiments, a method for mitigating errors caused by transients in a logic gate transistor comprises biasing, by a first stage of transistors, a second stage of transistors such that a voltage potential across terminals of each of the transistors of the second stage are at an equal voltage potential. The method further comprises biasing, by the second stage of transistors, the logic gate transistor such that a voltage potential across terminals of the logic gate transistor are at an equal voltage potential, thereby ensuring that the transients will not cause the logic gate transistor to erroneously change logic states when the logic gate transistor is in a logically off state.

Abstract: A rotary display device comprising one or more vertical arrays of light-emitting diodes (LEDs) are rotated and energized at a controlled rate so as to project a 360 degree floating image. The displayed images are viewable from all angles (i.e., 360 degrees). The LEDs and associated control electronics are rotated at a desired speed, e.g., between about 720 and about 3600 revolutions per minute, by an AC or DC motor. Display content is either pre-loaded to the rotary display or transferred to the rotary display during device operation via a cellular telephone, Wi-Fi, Bluetooth, etc. connection. The electrical power for the system, including the LED array and the control electronics, is provided via a contact-less rotary transformer that functions independently of the rotation speed.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the third settable memory element. The propagation delay through the third settable memory element is the only propagation delay of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Two settable memory elements, and a voting structure/settable memory element set an identical logical value into each settable memory element, and the voting structure/settable memory element. After the settable memory elements, and the voting structure/settable memory element are set, the voting structure/settable memory element with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the voting structure/settable memory element. The propagation delay through the voting structure/settable memory element is the only propagation delay of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the third settable memory element. The propagation delay through the third settable memory element is the only propagation delay of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Two settable memory elements, and a voting structure/settable memory element set an identical logical value into each settable memory element, and the voting structure/settable memory element. After the settable memory elements, and the voting structure/settable memory element are set, the voting structure/settable memory element with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the voting structure/settable memory element. The propagation delay through the voting structure/settable memory element is the only propagation delay of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch with storage node recovery. An input driver is connected to the input of three transfer gates. The output of each transfer gate is connected to a separate output of one of three feedback inverters. The transfer gates are controlled by two control inputs. The inputs of the three feedback inverters are connected the output of the forward inverter/majority voter. The output from each of the three feedback inverters are inputs to the forward inverter/majority voter. The output of the forward inverter/majority voter is connected to the input of the output driver. The output of the output driver is the output of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch with storage node recovery. An input driver is connected to the input of three transfer gates. The output of each transfer gate is connected to a separate output of one of three feedback inverters. The transfer gates are controlled by two control inputs. The inputs of the three feedback inverters are connected the output of the forward inverter/majority voter. The output from each of the three feedback inverters are inputs to the forward inverter/majority voter. The output of the forward inverter/majority voter is connected to the input of the output driver. The output of the output driver is the output of the triple redundant latch.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. An input driver is connected to the input of two transfer gates. The output of one transfer gate is connected to an I/O of a first latch and the output of the second transfer gate is connected to the I/O of a second latch. The I/O of the first latch is connected to a first input of a tristatable input inverter. The I/O of the second latch is connected to a second input of the tristatable input inverter. The output of the tristatable input inverter is connected to the I/O of a third latch and the input of an output driver.