Abstract: The present disclosure relates generally to antibody-drug conjugates comprising peptide-containing linkers and to methods of using these conjugates as therapeutics and/or diagnostics. Also disclosed herein are peptide-containing scaffolds useful to conjugate with a targeting moiety (e.g., an antibody), a drug, or both to produce the antibody-drug conjugates.

Abstract: The present disclosure provides a method for recycling urea-formaldehyde (UF) from a wood-based panel. In the present disclosure, the UF is depolymerized by an ultrasonic treatment, and depolymerized UF can be reused for UF manufacture and wood-based panel production. The recycled and treated UF can be repeatedly used in wood-based panel manufacture without affecting performances of the wood-based panel. UF-glued wood-based panels can be recycled, and a recycled wood-based panel raw material can replace at least 50% of a non-recycled wood-based raw material for particle board production without affecting performances of the wood-based panel.

Abstract: Integrated circuits such as programmable integrated circuits may have configuration random-access memory elements. The configuration random-access memory elements may be loaded with configuration data to customize programmable circuitry on the integrated circuits. Each memory element may have a bistable element that is powered using a positive power supply voltage and a negative power supply voltage. Programmable transistors in the programmable circuitry may have gates coupled to outputs of the bistable elements. The programmable transistors may have gate insulators that are thinner than gate insulators in the transistors of the bistable elements and may have threshold voltages of about zero volts. During operation, some of the configuration random-access memory elements may supply negative voltages to their associated programmable transistors so that the programmable transistors are provided with gate-source voltages of less than zero volts.

Abstract: An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

Abstract: In one embodiment of the invention, a test structure far testing the sufficiency of tunnel opening sizes in a non-volatile memory cell includes N write paths aligned substantially in parallel, each of the write paths beings individually programmable and M floating gates, each of the floating gates overlapping each of the multiple write paths to form a N column-by-M row array of Intersecting areas. An N column-by-M row array of tunnel openings is formed in the intersecting areas and between the floating gates and write paths, with the tunnel openings in each array column being of a same size and the tunnel openings in each array row being of different sizes. A read path coupled to the M floating gates is operable to detect a programmed write path if the tunnel openings formed over the programmed write path are of sufficient size to successfully couple the M floating gates to the programmed write path.

Abstract: A test structure is disclosed for determining the smallest acceptable tunnel opening size in a non-volatile memory cell. Additionally, defect density for one or more tunnel opening sizes may also be determined. In one aspect, the test structure has continuous strips of active area that are used to form a “control” path, a “read” path, and a “write” path. A dielectric layer is formed over the active strips. A one-dimensional array containing a number (N) of same-sized tunnel openings is formed on the write path. A layer of poly silicon is deposited over the dielectric and patterned into strips that are perpendicular to the active strips. The poly silicon strips are aligned with the tunnel openings and form a floating gate and sense device, which is capacitively coupled to external probe pads through the common “control” path.