Patents by Inventor Mao-Hua Yeh
Mao-Hua Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11747382Abstract: Testing equipment is used in an antenna testing process, and includes a testing head having a perforation, and a testing device having a cylinder. The cylinder is disposed in the perforation to act as a cavity for the antenna testing process. Therefore, only the cylinder needs to be replaced when the antenna testing process is performed on different devices under test, with the whole testing head intact.Type: GrantFiled: December 20, 2019Date of Patent: September 5, 2023Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Bo-Siang Fang, Kuang-Sheng Wang, Hsinjou Lin, Shao-Meng Sim, Mao-Hua Yeh
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Publication number: 20220005786Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Inventors: Lung-Yuan Wang, Feng Kao, Mao-Hua Yeh
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Patent number: 11152331Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.Type: GrantFiled: November 4, 2019Date of Patent: October 19, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lung-Yuan Wang, Feng Kao, Mao-Hua Yeh
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Patent number: 11081415Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.Type: GrantFiled: April 29, 2020Date of Patent: August 3, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
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Publication number: 20210123962Abstract: Testing equipment is used in an antenna testing process, and includes a testing head having a perforation, and a testing device having a cylinder. The cylinder is disposed in the perforation to act as a cavity for the antenna testing process. Therefore, only the cylinder needs to be replaced when the antenna testing process is performed on different devices under test, with the whole testing head intact.Type: ApplicationFiled: December 20, 2019Publication date: April 29, 2021Inventors: Bo-Siang Fang, Kuang-Sheng Wang, Hsinjou Lin, Shao-Meng Sim, Mao-Hua Yeh
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Publication number: 20200388591Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.Type: ApplicationFiled: November 4, 2019Publication date: December 10, 2020Inventors: Lung-Yuan Wang, Feng Kao, Mao-Hua Yeh
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Patent number: 10833394Abstract: An electronic package and a method for fabricating the same are provided. An antenna frame, a first electronic component, and a second electronic component electrically connected to the antenna frame are disposed on a lower side of a carrying structure. An antenna structure is disposed on an upper side of the carrying structure and is electrically connected to the first electronic component. Therefore, two different types of antennas are integrated into an identical electronic package. Such the electronic package bonded to a circuit can transmit signals with two different wavelengths, even if the electronic package does not have any area increased.Type: GrantFiled: August 7, 2019Date of Patent: November 10, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wen-Jung Tsai, Mao-Hua Yeh, Chih-Hsien Chiu, Ying-Chou Tsai, Chun-Chi Ke
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Publication number: 20200258802Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.Type: ApplicationFiled: April 29, 2020Publication date: August 13, 2020Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
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Publication number: 20200235462Abstract: An electronic package and a method for fabricating the same are provided. An antenna frame, a first electronic component, and a second electronic component electrically connected to the antenna frame are disposed on a lower side of a carrying structure. An antenna structure is disposed on an upper side of the carrying structure and is electrically connected to the first electronic component. Therefore, two different types of antennas are integrated into an identical electronic package. Such the electronic package bonded to a circuit can transmit signals with two different wavelengths, even if the electronic package does not have any area increased.Type: ApplicationFiled: August 7, 2019Publication date: July 23, 2020Inventors: Wen-Jung Tsai, Mao-Hua Yeh, Chih-Hsien Chiu, Ying-Chou Tsai, Chun-Chi Ke
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Patent number: 10679914Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.Type: GrantFiled: June 28, 2017Date of Patent: June 9, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
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Publication number: 20180254232Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.Type: ApplicationFiled: June 28, 2017Publication date: September 6, 2018Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
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Patent number: 9899308Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurrence of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.Type: GrantFiled: February 16, 2017Date of Patent: February 20, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
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Patent number: 9831191Abstract: A semiconductor substrate is provided, including a substrate body, a plurality of conductive through holes penetrating the substrate body, and at least one pillar disposed in the substrate body with the at least one pillar being free from penetrating the substrate body. When the semiconductor substrate is heated, the at least one pillar adjusts the expansion of upper and lower sides of the substrate body. Therefore, the upper and lower sides of the substrate body have substantially the same thermal deformation, and the substrate body is prevented from warpage.Type: GrantFiled: May 9, 2016Date of Patent: November 28, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chieh-Lung Lai, Mao-Hua Yeh, Hung-Yuan Li, Shih-Liang Peng, Chang-Lun Lu
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Publication number: 20170243834Abstract: A semiconductor substrate is provided, including a substrate body, a plurality of conductive through holes penetrating the substrate body, and at least one pillar disposed in the substrate body with the at least one pillar being free from penetrating the substrate body. When the semiconductor substrate is heated, the at least one pillar adjusts the expansion of upper and lower sides of the substrate body. Therefore, the upper and lower sides of the substrate body have substantially the same thermal deformation, and the substrate body is prevented from warpage.Type: ApplicationFiled: May 9, 2016Publication date: August 24, 2017Inventors: Chieh-Lung Lai, Mao-Hua Yeh, Hung-Yuan Li, Shih-Liang Peng, Chang-Lun Lu
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Publication number: 20170236783Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.Type: ApplicationFiled: April 28, 2017Publication date: August 17, 2017Inventors: Yi-Wei Liu, Yan-Heng Chen, Mao-Hua Yeh, Hung-Wen Liu, Yi-Che Lai
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Publication number: 20170229387Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.Type: ApplicationFiled: February 16, 2017Publication date: August 10, 2017Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
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Patent number: 9666536Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.Type: GrantFiled: December 2, 2015Date of Patent: May 30, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yi-Wei Liu, Yan-Heng Chen, Mao-Hua Yeh, Hung-Wen Liu, Yi-Che Lai
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Publication number: 20170148761Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.Type: ApplicationFiled: January 6, 2017Publication date: May 25, 2017Inventors: Guang-Hwa Ma, Shih-Kuang Chiu, Shih-Ching Chen, Chun-Chi Ke, Chang-Lun Lu, Chun-Hung Lu, Hsien-Wen Chen, Chun-Tang Lin, Yi-Che Lai, Chi-Hsin Chiu, Wen-Tsung Tseng, Tsung-Te Yuan, Lu-Yi Chen, Mao-Hua Yeh
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Patent number: 9607939Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.Type: GrantFiled: April 23, 2014Date of Patent: March 28, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
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Patent number: 9502335Abstract: A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.Type: GrantFiled: September 16, 2014Date of Patent: November 22, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chieh-Lung Lai, Hsien-Wen Chen, Hong-Da Chang, Mao-Hua Yeh