Patents by Inventor Mao-Rong Yeh

Mao-Rong Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • POLYSILOXANE RESIN, COATING COMPOSITION COMPRISING THE SAME, AND APPLICATION THEREOF
    Publication number: 20210032408
    Abstract: A polysiloxane resin, which includes a reaction product of the following: (a) a non-linear polysiloxane oligomer having a C1-3 alkoxy or a hydroxy group and a weight average molecular weight of about 500-6000; (b) a linear polysiloxane oligomer of Formula (II): and (c) a siloxane monomer, wherein R3, R4, and m are as defined in the specification. Also, a coating composition including the polysiloxane resin.
    Type: Application
    Filed: July 27, 2020
    Publication date: February 4, 2021
    Applicant: ETERNAL MATERIALS CO., LTD.
    Inventors: SHENG-WEI LIN, MAO-RONG YEH, AN-KAI WU, CHUN-HSIUNG CHANG
  • Method of forming ultra-shallow junctions in semiconductor devices
    Patent number: 10128115
    Abstract: A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Feng Nieh, Mao-Rong Yeh, Chun Hsiung Tsai, Chii-Ming Wu
  • Techniques for FinFET doping
    Patent number: 8785286
    Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
  • Techniques for FinFET doping
    Patent number: 8703593
    Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
  • Techniques for FinFET Doping
    Publication number: 20130280876
    Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.
    Type: Application
    Filed: June 14, 2013
    Publication date: October 24, 2013
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
  • High surface dopant concentration semiconductor device and method of fabricating
    Patent number: 8278196
    Abstract: The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: October 2, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Mao-Rong Yeh, Chun Hsiung Tsai, Tsung-Hung Lee, Da-Wen Lin, Tsz-Mei Kwok
  • METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS IN SEMICONDUCTOR DEVICES
    Publication number: 20120100686
    Abstract: A method of forming ultra-shallow lightly doped source/drain (LDD) regions of a CMOS transistor in a surface of a substrate includes the steps of providing a semiconductor substrate, providing a gate stack on the semiconductor substrate, performing a low temperature pocket implantation process on the substrate, performing a low temperature co-implanted ion implantation process on the substrate, and/or performing a low temperature lightly doped source/drain implantation process on the substrate.
    Type: Application
    Filed: October 20, 2010
    Publication date: April 26, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yuan LU, Li-Ping HUANG, Mao-Rong YEH, Chun-Feng NIEH
  • HIGH SURFACE DOPANT CONCENTRATION SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING
    Publication number: 20120018848
    Abstract: The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer.
    Type: Application
    Filed: July 21, 2010
    Publication date: January 26, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Mao-Rong Yeh, Chun Hsiung Tsai, Tsung-Hung Lee, Da-Wen Lin, Tsz-Mei Kwok
  • METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS IN SEMICONDUCTOR DEVICES
    Publication number: 20110212592
    Abstract: A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 1, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Feng NIEH, Mao-Rong Yeh, Chun Hsiung Tsai, Chii-Ming Wu
  • Techniques for FinFET Doping
    Publication number: 20110195555
    Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 11, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin