Abstract: According to one embodiment, a memory system includes a controller. The controller controls throttling to make a performance value of the memory system fall between a first performance value and a second performance value. The throttling limits the number of times of accesses per unit time to a nonvolatile memory. The first performance value is calculated based on a third performance value of the memory system and is greater than the third performance value. The third performance value is a value which is expected to be reached at a time when a first period has elapsed since the memory system started being used if throttling is not performed. The second performance value is provided between the first performance value and the third performance value.

Abstract: According to one embodiment, a memory system includes a controller. The controller controls throttling to make a performance value of the memory system fall between a first performance value and a second performance value. The throttling limits the number of times of accesses per unit time to a nonvolatile memory. The first performance value is calculated based on a third performance value of the memory system and is greater than the third performance value. The third performance value is a value which is expected to be reached at a time when a first period has elapsed since the memory system started being used if throttling is not performed. The second performance value is provided between the first performance value and the third performance value.

Abstract: According to one embodiment, a memory system includes a controller. The controller controls throttling to make a performance value of the memory system fall between a first performance value and a second performance value. The throttling limits the number of times of accesses per unit time to a nonvolatile memory. The first performance value is calculated based on a third performance value of the memory system and is greater than the third performance value. The third performance value is a value which is expected to be reached at a time when a first period has elapsed since the memory system started being used if throttling is not performed. The second performance value is provided between the first performance value and the third performance value.

Abstract: A memory system according to an embodiment includes a non-volatile memory and a controller configured to control the non-volatile memory. The controller includes an interface and a control unit. The interface receives, from a host, a first instruction to change a performance of the memory system as a performance control instruction. The control unit controls the memory system on the basis of the performance control instruction such that the number of parallel operations of parallel operating units which are operated in parallel in the memory system is changed.

Abstract: According to one embodiment, a memory system includes a controller. The controller controls throttling to make a performance value of the memory system fall between a first performance value and a second performance value. The throttling limits the number of times of accesses per unit time to a nonvolatile memory. The first performance value is calculated based on a third performance value of the memory system and is greater than the third performance value. The third performance value is a value which is expected to be reached at a time when a first period has elapsed since the memory system started being used if throttling is not performed. The second performance value is provided between the first performance value and the third performance value.

Abstract: A memory system according to an embodiment includes a non-volatile memory and a controller configured to control the non-volatile memory. The controller includes an interface and a control unit. The interface receives, from a host, a first instruction to change a performance of the memory system as a performance control instruction. The control unit controls the memory system on the basis of the performance control instruction such that the number of parallel operations of parallel operating units which are operated in parallel in the memory system is changed.

Abstract: A storage device can reduce time for diagnosis and allows the diagnosis to be conducted on the entire area of a memory. The storage device includes a temporary memory that temporarily stores for a storage medium, data written to and/or read from a host system by the storage medium; a memory manager that manages writing and/or reading performed on the temporary memory; a first storage memory that complements a difference in processing speed of writing and/or reading between the host system and the temporary memory; and a second storage memory that complements a difference in processing speed of writing and reading between the storage medium and the temporary memory. The memory manager has a comparator, which compares the diagnostic data stored in the first storage memory with the read data stored in the second storage memory, and determines that there is an abnormality if a comparison result is inconsistent.