Patents by Inventor Marat GERSHOIG
Marat GERSHOIG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133951Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Saman M.I. ADHAM, Marat GERSHOIG
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Publication number: 20240055066Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors such that at least one input vector of the plurality of input vectors is transmitted to the memory macro in each of a plurality of cycles, receiving in each of the plurality of cycles, an output data from the memory macro. The output data is generated by the memory macro in response to processing the at least one input vector. The BIST also includes comparing the output data in each of the plurality of cycles with a signature value and determining whether the memory macro is normal or faulty based upon the comparison.Type: ApplicationFiled: October 13, 2023Publication date: February 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ted Wong, Saman Adham, Marat Gershoig, Vineet Joshi
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Patent number: 11899064Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.Type: GrantFiled: December 13, 2022Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham, Marat Gershoig
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Patent number: 11823758Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors such that at least one input vector of the plurality of input vectors is transmitted to the memory macro in each of a plurality of cycles, receiving in each of the plurality of cycles, an output data from the memory macro. The output data is generated by the memory macro in response to processing the at least one input vector. The BIST also includes comparing the output data in each of the plurality of cycles with a signature value and determining whether the memory macro is normal or faulty based upon the comparison.Type: GrantFiled: September 9, 2021Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Saman Adham, Ted Wong, Marat Gershoig, Vineet Joshi
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Publication number: 20230113905Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.Type: ApplicationFiled: December 13, 2022Publication date: April 13, 2023Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Saman M.I. ADHAM, Marat GERSHOIG
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Patent number: 11549984Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.Type: GrantFiled: December 23, 2019Date of Patent: January 10, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham, Marat Gershoig
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Publication number: 20220254429Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors. One input vector is transmitted to the memory macro in each of a plurality of cycles. Each of the plurality of input vectors is associated with a bit width. Generating the input vector includes generating a partial input vector of half the bit width and transmitting the partial input vector to each of a first half of the memory macro and a second half of the memory macro. The method also includes receiving, in each of the plurality of cycles, an output data from the memory macro, such that the output data is generated by the memory macro in response to processing the partial input vector, comparing the output data with a signature value, and determining whether the memory macro is normal or faulty based upon the comparison.Type: ApplicationFiled: September 9, 2021Publication date: August 11, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ted Wong, Saman Adham, Marat Gershoig
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Publication number: 20220254428Abstract: Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors such that at least one input vector of the plurality of input vectors is transmitted to the memory macro in each of a plurality of cycles, receiving in each of the plurality of cycles, an output data from the memory macro. The output data is generated by the memory macro in response to processing the at least one input vector. The BIST also includes comparing the output data in each of the plurality of cycles with a signature value and determining whether the memory macro is normal or faulty based upon the comparison.Type: ApplicationFiled: September 9, 2021Publication date: August 11, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Saman Adham, Ted Wong, Marat Gershoig, Vineet Joshi
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Publication number: 20200124668Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.Type: ApplicationFiled: December 23, 2019Publication date: April 23, 2020Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Saman M.I ADHAM, Marat GERSHOIG
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Patent number: 10539617Abstract: A device comprises a first die; and a second die stacked below the first die with interconnections between the first die and the second die. A least one of the first die or the second die has a circuit for performing a function and provides a functional path. Each of the first and second dies comprise a plurality of latches, including a respective latch corresponding to each one of the interconnections; and a plurality of multiplexers. Each multiplexer is connected to a respective one of the plurality of latches and arranged for receiving and selecting one of a scan test pattern or a signal from the functional path for outputting during a scan chain test of the first die and second die.Type: GrantFiled: June 2, 2016Date of Patent: January 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham, Marat Gershoig
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Publication number: 20170350939Abstract: A device comprises a first die; and a second die stacked below the first die with interconnections between the first die and the second die. A least one of the first die or the second die has a circuit for performing a function and provides a functional path. Each of the first and second dies comprise a plurality of latches, including a respective latch corresponding to each one of the interconnections; and a plurality of multiplexers. Each multiplexer is connected to a respective one of the plurality of latches and arranged for receiving and selecting one of a scan test pattern or a signal from the functional path for outputting during a scan chain test of the first die and second die.Type: ApplicationFiled: June 2, 2016Publication date: December 7, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Saman M.I. ADHAM, Marat GERSHOIG