Patents by Inventor Marat Teplitsky

Marat Teplitsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9582406
    Abstract: Method and system for automatically generating executable system-level tests. The method includes obtaining a system design including interrelation between components of the system design, actions the components are operable to perform, and constraints relating to the performance of the actions; receiving at least an initial action input to be tested; automatically generating a complete test scenario including: solving a logic layer CSP, including automatically scheduling actions and data paths of the test scenario, and assigning values to logic attributes of the actions and data, satisfying constraints relating to the logic layer, and solving a data layer CSP, satisfying constraints relating to data attributes taking into account the constraints relating to the logic layer; and generating the executable system-level test by assembling the initial action and the set of scheduled actions and data paths and the data attributes.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: February 28, 2017
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Marat Teplitsky, Matan Vax, Amit Metodi
  • Patent number: 9514035
    Abstract: A method, system and computer readable medium for coverage driven generation of stimuli for DUT verification. The method may include receiving, via an input device, a generation model and a coverage model from a user. The method may also include using a processor, identifying a coverage item in the coverage model and finding a corresponding element in the generation model corresponding to the coverage item. The method may further include using a processor translating a coverage requirement associated with the coverage item into a distribution directive; and using a processor, solving the generation model with the distribution directive on the corresponding element, to obtain a set of stimuli.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 6, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Marat Teplitsky, Raz Azaria, Amit Metodi, Yael Kinderman
  • Patent number: 9239773
    Abstract: A method for debugging a program that includes declarative code and procedural code includes presenting to a user on an output device data relating to execution of the procedural code and data relating to execution of the declarative code. The data is presented in the form of a sequence of execution events corresponding to a computational flow of an execution of the program.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: January 19, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Marat Teplitsky, Reuven Naveh, Rotem Gubes, Raz Azaria
  • Patent number: 9189743
    Abstract: The present disclosure relates to a computer-implemented method for iteratively solving a constraint satisfaction problem. The method may include assigning a value to each of one or more variables associated with the constraint satisfaction problem, each of the one or more variables having a first domain. The method may also include identifying an invalid solution resulting from a first value assigned to a first variable. The method may further include replacing the first value with a second value assigned to the first variable. The method may also include, upon identifying the invalid solution, generating a second domain larger than the first domain.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: November 17, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Marat Teplitsky, Efrat Gavish, Kalev Alpernas
  • Patent number: 8719771
    Abstract: Disclosed is a method, system, and computer program product that reduces the size of a failing test. A tree is created from the test's programming code, where the tree represents the syntactical and the semantic bounds between the programming code elements. By analyzing this tree and iteratively pruning the irrelevant sub-trees it is possible to eliminate many non necessary parts of the code, and recreate a new legal test, which represents the same error, but is potentially much smaller and therefore easier to understand and debug.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: May 6, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Meir Ovadia, Marat Teplitsky, Rodion Melnikov
  • Patent number: 8156474
    Abstract: A method, system, and computer program product are disclosed for automatic test generation for a compiler. In one approach, the method, system and computer program product represent a test case for the compiler in a structure with one or more elements of a programming language, associate at least one syntactic rule and semantic rule with the one or more elements in the structure, create a test with the structure compiling the test with the compiler, and display results of the test.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 10, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Marat Teplitsky, Meir Ovadia, Noa Gradovich
  • Publication number: 20110078651
    Abstract: Disclosed is a method, system, and computer program product that reduces the size of a failing test. A tree is created from the test's programming code, where the tree represents the syntactical and the semantic bounds between the programming code elements. By analyzing this tree and iteratively pruning the irrelevant sub-trees it is possible to eliminate many non necessary parts of the code, and recreate a new legal test, which represents the same error, but is potentially much smaller and therefore easier to understand and debug.
    Type: Application
    Filed: September 28, 2009
    Publication date: March 31, 2011
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Meir OVADIA, Marat TEPLITSKY, Rodion MELNIKOV
  • Publication number: 20090172649
    Abstract: A method, system, and computer program product are disclosed for automatic test generation for a compiler. In one approach, the method, system and computer program product represent a test case for the compiler in a structure with one or more elements of a programming language, associate at least one syntactic rule and semantic rule with the one or more elements in the structure, create a test with the structure compiling the test with the compiler, and display results of the test.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Applicant: CADENCE DESIGN SYSTEM, INC.
    Inventors: Marat Teplitsky, Meir Ovadia, Noa Gradovitch