Abstract: The disclosed apparatus may include (1) at least one alignment pin that (A) is placed proximate to a component on a circuit board and (B) is secured proximate to the component on the circuit board and (2) at least one heatsink that (A) is placed atop the component after completion of a reflow process in which the component is soldered to the circuit board, (B) is aligned by the alignment pin such that the heatsink resides in a specific position atop the component, and (C) absorbs heat dissipated by the component when the component is operational. Various other apparatuses, systems, and methods are also disclosed.

Abstract: The disclosed apparatus may include (1) at least one alignment pin that (A) is placed proximate to a component on a circuit board and (B) is secured proximate to the component on the circuit board and (2) at least one heatsink that (A) is placed atop the component after completion of a reflow process in which the component is soldered to the circuit board, (B) is aligned by the alignment pin such that the heatsink resides in a specific position atop the component, and (C) absorbs heat dissipated by the component when the component is operational. Various other apparatuses, systems, and methods are also disclosed.

Abstract: The disclosed apparatus may include (1) a removable stiffening brace that (A) temporarily interfaces with a bottom surface of a circuit board during a reflow process in which at least one component is soldered to the circuit board and (B) provides structural support to the circuit board to prevent the circuit board from warping during the reflow process and (2) at least one fastener that secures the removable stiffening brace to the bottom surface of the circuit board during the reflow process. Various other apparatuses, systems, and methods are also disclosed.

Abstract: The disclosed apparatus may include (1) a stiffening brace that (A) is coupled to a top surface of a lidless integrated circuit and (B) includes at least one joint and (2) a removable lid that (A) interfaces with the stiffening brace at the joint, (B) temporarily sits atop the stiffening brace during a reflow process in which a bottom surface of the lidless integrated circuit is soldered to a circuit board, and (C) provides structural support to the lidless integrated circuit to impede the lidless integrated circuit from warping during the reflow process. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A method and apparatus to provide electrostatic discharge (ESD) protection to electronic circuits using a combination of low voltage and high voltage transistors.

Abstract: An IGFET is presented which includes a relatively low resistance path across the source-substrate junction to prevent parasitic bipolar effects while maintaining high component density in integrated circuits. The low resistance path across the source-substrate junction is formed by various methods including damaging the crystal structure at the junction interface, supplementing the damaged junction with a heavily doped region underlying the source region and spiking metallurgy. A particular application of the invention allows the prevention of latchup in CMOS devices. The invention also allows the source region of an IGFET to serve the dual functions of a source for a MOSFET as well as an ohmic contact to the underlying well or substrate.

Abstract: Protection of the thin gate oxide of MOS field effect transistors from irreversible puncture due to undesired high voltages and currents, generated by electrostatic discharge through handling or otherwise, is provided by a two stage circuit that operates to shunt thousands or tens of volts around the protected transistors. A first stage, employing a thick field effect transistor, protects against the very high voltage. A second stage, employing a thin field effect transistor, protects against lower but still excessive voltage. The protection circuit is formed as part of an integrated circuit chip by surrounding the lead bonding pad to which the protected transistors are connected.

Abstract: A circuit arrangement is provided for a command source directing operation of a subsequent circuit. This command source circuit, based on using cross-coupled transistors, is electrically isolated from the subsequent circuit when no commands are being generated, and provides an output of constant polarity for input command signals of either constant or varying polarity.

Abstract: Protection of the thin gate oxide of MOS field effect transistors from irreversible puncture due to undesired high voltages and currents, generated by electrostatic discharge through handling or otherwise, is provided by a two stage circuit that operates to shunt thousands or tens of volts around the protected transistors. A first stage, employing a thick field effect transistor, protects against the very high voltage. A second stage, employing a thin field effect transistor, protects against lower but still excessive voltage. The protection circuit is formed as part of an integrated circuit chip by surrounding the lead bonding pad to which the protected transistors are connected.

Abstract: An electronic switching circuit is provided for controlling transfer of electrical power from an alternating polarity electrical power supply to a load means through use of a field-effect transistor device as the primary power controlling element. A bypass means is used to provide shunting between one of the terminating regions of the field-effect transistor device and its substrate in situations where the field-effect transistor device is passing substantial current.

Abstract: Electronic switching circuit is provided for controlling transfer of electrical power from an alternating polarity electrical power supply to a load means through use of a field-effect transistor device as the controlling element. A circuit arrangement is provided for switching into the "on" condition primary power control field-effect transistor device only when the voltage thereacross is at a relatively low value and for switching into the "off" condition this device in a gradual manner, relatively slowly reducing currents flowing therethrough. A circuit arrangement for a command source directing operation of the primary power transfer control field-effect transistor device provides command source isolation.