Abstract: A method and apparatus for resetting memory state when power is applied to the system. The memory has memory elements, a refresh clock and a refresh counter for counting refresh cycles and providing refresh signals to the memory elements, the memory elements and refresh means being connected from the power system and from a battery back-up means. A state detection means is connected from the refresh counter for detecting a change in state of the refresh counter to a state equivalent to the reset state of the refresh counter and asserting a state change signal. A means responsive to the state change signal and to the occurrence of the reset signal provides a memory controller reset signal, so that the memory controller reset signal occurs in synchronization with the change of state of the refresh counter to a state equivalent to the refresh counter reset state.

Abstract: In accordance with the present invention, there is provided a system for logging an error that occurred in a multi-chip memory storage device in a data processing system. The system has a mechanism for detecting an error and for receiving data and check bits associated therewith. The mechanism for detecting an error generates syndrome bits as a function of the data and of the check bits. Connected to the error detecting mechanism is an error logging mechanism which is adapted to receive the syndrome bits and to determine the chip in which the error occurred.

Abstract: A system and method for detecting an error that occurred in a multi-chip memory storage device in a data processing system. The system detects an error and receives data and check bits associated therewith. A process that uses the principle of scrubbing and incorporates high speed error flags distinguishes between hard and soft errors.