Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

Abstract: An analog-to-digital converter (“ADC”). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

Abstract: An analog-to-digital converter (“ADC”) is disclosed. The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.